[xen staging] arm,smmu: match start level of page table walk with P2M

[patchbot@xxxxxxx]

commit 9ae1197582798b394d696cff94c4d742319bdbbf
Author:     Laurentiu Tudor <laurentiu.tudor@xxxxxxx>
AuthorDate: Fri Oct 2 13:33:44 2020 +0300
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Fri Oct 2 10:21:56 2020 -0700

    arm,smmu: match start level of page table walk with P2M
    
    Don't hardcode the lookup start level of the page table walk to 1
    and instead match the one used in P2M. This should fix scenarios
    involving SMMU where the start level is different than 1.
    In order for the SMMU driver to also compile on arm32 move the
    P2M_ROOT_LEVEL in the p2m header file (while at it, for
    consistency also P2M_ROOT_ORDER) and use the macro in the smmu
    driver.
    
    Signed-off-by: Laurentiu Tudor <laurentiu.tudor@xxxxxxx>
    Acked-by: Julien Grall <jgrall@xxxxxxxxxx>
    Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/arch/arm/p2m.c                 |  9 ++-------
 xen/drivers/passthrough/arm/smmu.c |  2 +-
 xen/include/asm-arm/p2m.h          | 11 +++++++++++
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index ce59f2b503..4eeb867ca1 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -17,17 +17,12 @@
 #define INVALID_VMID 0 /* VMID 0 is reserved */
 
 #ifdef CONFIG_ARM_64
-static unsigned int __read_mostly p2m_root_order;
-static unsigned int __read_mostly p2m_root_level;
-#define P2M_ROOT_ORDER    p2m_root_order
-#define P2M_ROOT_LEVEL p2m_root_level
+unsigned int __read_mostly p2m_root_order;
+unsigned int __read_mostly p2m_root_level;
 static unsigned int __read_mostly max_vmid = MAX_VMID_8_BIT;
 /* VMID is by default 8 bit width on AArch64 */
 #define MAX_VMID       max_vmid
 #else
-/* First level P2M is always 2 consecutive pages */
-#define P2M_ROOT_LEVEL 1
-#define P2M_ROOT_ORDER    1
 /* VMID is always 8 bit width on AArch32 */
 #define MAX_VMID        MAX_VMID_8_BIT
 #endif
diff --git a/xen/drivers/passthrough/arm/smmu.c 
b/xen/drivers/passthrough/arm/smmu.c
index 06f9bda47d..b8321f5d8d 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -1152,7 +1152,7 @@ static void arm_smmu_init_context_bank(struct 
arm_smmu_domain *smmu_domain)
              (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 
        if (!stage1)
-               reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
+               reg |= (2 - P2M_ROOT_LEVEL) << TTBCR_SL0_SHIFT;
 
        writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 
diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h
index 5fdb6e8183..28ca9a838e 100644
--- a/xen/include/asm-arm/p2m.h
+++ b/xen/include/asm-arm/p2m.h
@@ -13,6 +13,17 @@
 /* Holds the bit size of IPAs in p2m tables.  */
 extern unsigned int p2m_ipa_bits;
 
+#ifdef CONFIG_ARM_64
+extern unsigned int p2m_root_order;
+extern unsigned int p2m_root_level;
+#define P2M_ROOT_ORDER    p2m_root_order
+#define P2M_ROOT_LEVEL p2m_root_level
+#else
+/* First level P2M is always 2 consecutive pages */
+#define P2M_ROOT_ORDER    1
+#define P2M_ROOT_LEVEL 1
+#endif
+
 struct domain;
 
 extern void memory_type_changed(struct domain *);
--
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