[qemu-xen staging-4.14] hw/riscv: Allow 64 bit access to SiFive CLINT

[patchbot@xxxxxxx]

commit 182be029628068dc7739b496df63f073f2aa8ae3
Author:     Alistair Francis <alistair.francis@xxxxxxx>
AuthorDate: Tue Jun 30 13:12:11 2020 -0700
Commit:     Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
CommitDate: Thu Aug 27 00:03:16 2020 -0500

    hw/riscv: Allow 64 bit access to SiFive CLINT
    
    Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
    "memory: Revert "memory: accept mismatching sizes in
    memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
    accesses to the CLINT and QEMU would trigger a fault. Fix this failure
    by allowing 8 byte accesses.
    
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
    Reviewed-by: LIU Zhiwei<zhiwei_liu@xxxxxxxxx>
    Message-Id: 
<122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@xxxxxxx>
    (cherry picked from commit 70b78d4e71494c90d2ccb40381336bc9b9a22f79)
    Signed-off-by: Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
---
 hw/riscv/sifive_clint.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index e933d35092..a2a4b7d752 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -180,7 +180,7 @@ static const MemoryRegionOps sifive_clint_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,
-        .max_access_size = 4
+        .max_access_size = 8
     }
 };
 
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