[qemu-xen staging] RISC-V: Support 64 bit start address

[patchbot@xxxxxxx]

commit 8590f53661ec678fd3aa97b4da212b0c00056c2e
Author:     Atish Patra <atish.patra@xxxxxxx>
AuthorDate: Wed Jul 1 11:39:49 2020 -0700
Commit:     Alistair Francis <alistair.francis@xxxxxxx>
CommitDate: Mon Jul 13 17:25:37 2020 -0700

    RISC-V: Support 64 bit start address
    
    Even though the start address in ROM code is declared as a 64 bit address
    for RV64, it can't be used as upper bits are set to zero in ROM code.
    
    Update the ROM code correctly to reflect the 64bit value.
    
    Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
    Reviewed-by: Bin Meng <bin.meng@xxxxxxxxxxxxx>
    Tested-by: Bin Meng <bin.meng@xxxxxxxxxxxxx>
    Message-Id: <20200701183949.398134-5-atish.patra@xxxxxxx>
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
---
 hw/riscv/boot.c     | 6 +++++-
 hw/riscv/sifive_u.c | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index feff6e3f4e..4c6c101ff1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr 
rom_base,
                                uint32_t fdt_load_addr, void *fdt)
 {
     int i;
+    uint32_t start_addr_hi32 = 0x00000000;
 
+    #if defined(TARGET_RISCV64)
+    start_addr_hi32 = start_addr >> 32;
+    #endif
     /* reset vector */
     uint32_t reset_vec[10] = {
         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
@@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr 
rom_base,
 #endif
         0x00028067,                  /*     jr     t0 */
         start_addr,                  /* start: .dword */
-        0x00000000,
+        start_addr_hi32,
         fdt_load_addr,               /* fdt_laddr: .dword */
         0x00000000,
                                      /* fw_dyn: */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 46e6ed90ca..6595ab3f87 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+    uint32_t start_addr_hi32 = 0x00000000;
     int i;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
@@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine)
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
                                    machine->ram_size, s->fdt);
+    #if defined(TARGET_RISCV64)
+    start_addr_hi32 = start_addr >> 32;
+    #endif
 
     /* reset vector */
     uint32_t reset_vec[11] = {
@@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine)
 #endif
         0x00028067,                    /*     jr     t0 */
         start_addr,                    /* start: .dword */
-        0x00000000,
+        start_addr_hi32,
         fdt_load_addr,                 /* fdt_laddr: .dword */
         0x00000000,
                                        /* fw_dyn: */
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging