[qemu-xen staging] hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ

[patchbot@xxxxxxx]

commit 9e60d759d38d1faae1d85de2c53411e635be3cf2
Author:     Peter Maydell <peter.maydell@xxxxxxxxxx>
AuthorDate: Mon Aug 3 17:55:03 2020 +0100
Commit:     Peter Maydell <peter.maydell@xxxxxxxxxx>
CommitDate: Mon Aug 3 17:55:03 2020 +0100

    hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for 
SYSRESETREQ
    
    The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
    when the guest sets the SYSRESETREQ bit in the AIRCR register.  This
    matches the hardware design (where the CPU has a signal of this name
    and it is up to the SoC to connect that up to an actual reset
    mechanism), but in QEMU it mostly results in duplicated code in SoC
    objects and bugs where SoC model implementors forget to wire up the
    SYSRESETREQ line.
    
    Provide a default behaviour for the case where SYSRESETREQ is not
    actually connected to anything: use qemu_system_reset_request() to
    perform a system reset.  This will allow us to remove the
    implementations of SYSRESETREQ handling from the boards where that's
    exactly what it does, and also fixes the bugs in the board models
    which forgot to wire up the signal:
    
     * microbit
     * mps2-an385
     * mps2-an505
     * mps2-an511
     * mps2-an521
     * musca-a
     * musca-b1
     * netduino
     * netduinoplus2
    
    We still allow the board to wire up the signal if it needs to, in case
    we need to model more complicated reset controller logic or to model
    buggy SoC hardware which forgot to wire up the line itself. But
    defaulting to "reset the system" is more often going to be correct
    than defaulting to "do nothing".
    
    Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
    Reviewed-by: Philippe Mathieu-Daudé <f4bug@xxxxxxxxx>
    Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
    Message-id: 20200728103744.6909-3-peter.maydell@xxxxxxxxxx
---
 hw/intc/armv7m_nvic.c   | 17 ++++++++++++++++-
 include/hw/arm/armv7m.h |  4 +++-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3c4b6e6d70..277a98b87b 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -19,6 +19,7 @@
 #include "hw/intc/armv7m_nvic.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "sysemu/runstate.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
 #include "exec/memop.h"
@@ -64,6 +65,20 @@ static const uint8_t nvic_id[] = {
     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
 };
 
+static void signal_sysresetreq(NVICState *s)
+{
+    if (qemu_irq_is_connected(s->sysresetreq)) {
+        qemu_irq_pulse(s->sysresetreq);
+    } else {
+        /*
+         * Default behaviour if the SoC doesn't need to wire up
+         * SYSRESETREQ (eg to a system reset controller of some kind):
+         * perform a system reset via the usual QEMU API.
+         */
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+    }
+}
+
 static int nvic_pending_prio(NVICState *s)
 {
     /* return the group priority of the current pending interrupt,
@@ -1524,7 +1539,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, 
uint32_t value,
             if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
                 if (attrs.secure ||
                     !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
-                    qemu_irq_pulse(s->sysresetreq);
+                    signal_sysresetreq(s);
                 }
             }
             if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index d2c74d3872..a30e3c6471 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -35,7 +35,9 @@ typedef struct {
 
 /* ARMv7M container object.
  * + Unnamed GPIO input lines: external IRQ lines for the NVIC
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
+ *   If this GPIO is not wired up then the NVIC will default to performing
+ *   a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
  * + Property "cpu-type": CPU type to instantiate
  * + Property "num-irq": number of external IRQ lines
  * + Property "memory": MemoryRegion defining the physical address space
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging