[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [qemu-xen master] target/riscv: fix vill bit index in vtype register
commit fbcbafa2c1c33ae6630e7717f7f4141befb5b31a Author: Frank Chang <frank.chang@xxxxxxxxxx> AuthorDate: Fri Jul 10 18:48:18 2020 +0800 Commit: Alistair Francis <alistair.francis@xxxxxxx> CommitDate: Mon Jul 13 17:25:37 2020 -0700 target/riscv: fix vill bit index in vtype register vill bit is at vtype[XLEN-1]. Signed-off-by: Frank Chang <frank.chang@xxxxxxxxxx> Reviewed-by: Richard Henderson <richard.henderson@xxxxxxxxxx> Message-Id: <20200710104920.13550-5-frank.chang@xxxxxxxxxx> Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx> --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eef20ca6e5..a804a5d0ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; -- generated by git-patchbot for /home/xen/git/qemu-xen.git#master
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