[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen stable-4.14] x86emul: fix PINSRW and adjust other {,V}PINSR*
commit fc8fab1bb4d3a16914d8e7f6e288e946e68d5a41 Author: Jan Beulich <jbeulich@xxxxxxxx> AuthorDate: Wed Nov 4 11:02:30 2020 +0100 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Wed Nov 4 11:02:30 2020 +0100 x86emul: fix PINSRW and adjust other {,V}PINSR* The use of simd_packed_int together with no further update to op_bytes has lead to wrong signaling of #GP(0) for PINSRW without a 16-byte aligned memory operand. Use simd_none instead and override it after general decoding with simd_other, like is done for the B/D/Q siblings. While benign, for consistency also use DstImplicit instead of DstReg in x86_decode_twobyte(). PINSR{B,D,Q} also had a stray (redundant) get_fpu() invocation, which gets dropped. For further consistency also - use src.bytes instead of op_bytes in relevant memcpy() invocations, - avoid the pointless updating of op_bytes (all we care about later is that the value be less than 16). Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> master commit: 06f0598b41f23c9e4cf7d8c5a05b282de92f3a35 master date: 2020-10-23 18:03:18 +0200 --- xen/arch/x86/x86_emulate/x86_emulate.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index ee6341b1b7..9b29548e2d 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -362,7 +362,7 @@ static const struct twobyte_table { [0xc1] = { DstMem|SrcReg|ModRM }, [0xc2] = { DstImplicit|SrcImmByte|ModRM, simd_any_fp, d8s_vl }, [0xc3] = { DstMem|SrcReg|ModRM|Mov }, - [0xc4] = { DstReg|SrcImmByte|ModRM, simd_packed_int, 1 }, + [0xc4] = { DstImplicit|SrcImmByte|ModRM, simd_none, 1 }, [0xc5] = { DstReg|SrcImmByte|ModRM|Mov }, [0xc6] = { DstImplicit|SrcImmByte|ModRM, simd_packed_fp, d8s_vl }, [0xc7] = { ImplicitOps|ModRM }, @@ -2784,7 +2784,7 @@ x86_decode_twobyte( /* fall through */ case X86EMUL_OPC_VEX_66(0, 0xc4): /* vpinsrw */ case X86EMUL_OPC_EVEX_66(0, 0xc4): /* vpinsrw */ - state->desc = DstReg | SrcMem16; + state->desc = DstImplicit | SrcMem16; break; case 0xf0: @@ -8587,6 +8587,7 @@ x86_emulate( generate_exception_if(vex.l, EXC_UD); memcpy(mmvalp, &src.val, 2); ea.type = OP_MEM; + state->simd_size = simd_other; goto simd_0f_int_imm8; #ifndef X86EMUL_NO_SIMD @@ -8601,9 +8602,8 @@ x86_emulate( host_and_vcpu_must_have(avx512bw); if ( !mode_64bit() ) evex.w = 0; - memcpy(mmvalp, &src.val, op_bytes); + memcpy(mmvalp, &src.val, src.bytes); ea.type = OP_MEM; - op_bytes = src.bytes; d = SrcMem16; /* Fake for the common SIMD code below. */ state->simd_size = simd_other; goto avx512f_imm8_no_sae; @@ -10766,10 +10766,8 @@ x86_emulate( case X86EMUL_OPC_66(0x0f3a, 0x20): /* pinsrb $imm8,r32/m8,xmm */ case X86EMUL_OPC_66(0x0f3a, 0x22): /* pinsr{d,q} $imm8,r/m,xmm */ host_and_vcpu_must_have(sse4_1); - get_fpu(X86EMUL_FPU_xmm); - memcpy(mmvalp, &src.val, op_bytes); + memcpy(mmvalp, &src.val, src.bytes); ea.type = OP_MEM; - op_bytes = src.bytes; d = SrcMem16; /* Fake for the common SIMD code below. */ state->simd_size = simd_other; goto simd_0f3a_common; @@ -10779,9 +10777,8 @@ x86_emulate( generate_exception_if(vex.l, EXC_UD); if ( !mode_64bit() ) vex.w = 0; - memcpy(mmvalp, &src.val, op_bytes); + memcpy(mmvalp, &src.val, src.bytes); ea.type = OP_MEM; - op_bytes = src.bytes; d = SrcMem16; /* Fake for the common SIMD code below. */ state->simd_size = simd_other; goto simd_0f_int_imm8; -- generated by git-patchbot for /home/xen/git/xen.git#stable-4.14
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