[xen staging] x86/vioapic: fix usage of index in place of GSI in vioapic_write_redirent

[patchbot@xxxxxxx]

commit 3ae469af8e680df31eecd0a2ac6a83b58ad7ce53
Author:     Roger Pau Monné <roge.rpau@xxxxxxxxxx>
AuthorDate: Mon Nov 30 14:06:38 2020 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Nov 30 14:06:38 2020 +0100

    x86/vioapic: fix usage of index in place of GSI in vioapic_write_redirent
    
    The usage of idx instead of the GSI in vioapic_write_redirent when
    accessing gsi_assert_count can cause a PVH dom0 with multiple
    vIO-APICs to lose interrupts in case a pin of a IO-APIC different than
    the first one is unmasked with pending interrupts.
    
    Switch to use gsi instead to fix the issue.
    
    Fixes: 9f44b08f7d0e4 ('x86/vioapic: introduce support for multiple vIO 
APICS')
    Reported-by: Manuel Bouyer <bouyer@xxxxxxxxxxxxxxx>
    Signed-off-by: Roger Pau Monné <roge.rpau@xxxxxxxxxx>
    Tested-by: Manuel Bouyer <bouyer@xxxxxxxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/hvm/vioapic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 67d4a6237f..e64abee7a9 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -260,7 +260,7 @@ static void vioapic_write_redirent(
         pent->fields.remote_irr = 0;
     else if ( !ent.fields.mask &&
               !ent.fields.remote_irr &&
-              hvm_irq->gsi_assert_count[idx] )
+              hvm_irq->gsi_assert_count[gsi] )
     {
         pent->fields.remote_irr = 1;
         vioapic_deliver(vioapic, idx);
--
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