[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging] x86/msr: Don't inject #GP when trying to read FEATURE_CONTROL
commit ca88a43e660c75796656a544e54a648c60d26ef0 Author: Roger Pau Monne <roger.pau@xxxxxxxxxx> AuthorDate: Tue Dec 29 17:58:01 2020 +0100 Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> CommitDate: Tue Jan 26 12:56:28 2021 +0000 x86/msr: Don't inject #GP when trying to read FEATURE_CONTROL Windows 10 will triple fault if #GP is injected when attempting to read the FEATURE_CONTROL MSR on Intel or compatible hardware. Fix this by injecting a #GP only when the vendor doesn't support the MSR, even if there are no features to expose. Fixes: 39ab598c50a2 ('x86/pv: allow reading FEATURE_CONTROL MSR') Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Acked-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> [Extended comment] Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- xen/arch/x86/msr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index be8e363862..8ed0b4e982 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -176,7 +176,16 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) switch ( msr ) { case MSR_IA32_FEATURE_CONTROL: - if ( !cp->basic.vmx && !vmce_has_lmce(v) ) + /* + * Architecturally, availability of this MSR is enumerated by the + * visibility of any sub-feature. However, Win10 in at some + * configurations performs a read before setting up a #GP handler. + * + * The MSR has existed on all Intel parts since before the 64bit days, + * and is implemented by other vendors. + */ + if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI)) ) goto gp_fault; *val = IA32_FEATURE_CONTROL_LOCK; -- generated by git-patchbot for /home/xen/git/xen.git#staging
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