[xen staging-4.13] x86/vioapic: check IRR before attempting to inject interrupt after EOI

[patchbot@xxxxxxx]

commit 8b4f699b65db279a04c09dd30425f3830d6ba654
Author:     Roger Pau Monné <roger.pau@xxxxxxxxxx>
AuthorDate: Fri Mar 5 15:40:32 2021 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Mar 5 15:40:32 2021 +0100

    x86/vioapic: check IRR before attempting to inject interrupt after EOI
    
    In vioapic_update_EOI the irq_lock will be dropped in order to forward
    the EOI to the dpci handler, so there's a window between clearing IRR
    and checking if the line is asserted where IRR can change behind our
    back.
    
    Fix this by checking whether IRR is set before attempting to inject a
    new interrupt.
    
    Fixes: 06e3f8f2766 ('vt-d: Do dpci eoi outside of irq_lock.')
    Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: ba584fb1a26c058ebd0e6a2779287b3e4400415c
    master date: 2021-01-22 12:13:05 +0100
---
 xen/arch/x86/hvm/vioapic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index da03b4d4b3..35717edf73 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -544,7 +544,7 @@ void vioapic_update_EOI(struct domain *d, u8 vector)
             }
 
             if ( (ent->fields.trig_mode == VIOAPIC_LEVEL_TRIG) &&
-                 !ent->fields.mask &&
+                 !ent->fields.mask && !ent->fields.remote_irr &&
                  hvm_irq->gsi_assert_count[vioapic->base_gsi + pin] )
             {
                 ent->fields.remote_irr = 1;
--
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