[xen staging] x86/AMD: expose HWCR.TscFreqSel to guests

[patchbot@xxxxxxx]

commit 14b95b3b8546db201e7efd0636ae0e215fae98f3
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Mar 12 12:03:06 2021 +0100
Commit:     Ian Jackson <iwj@xxxxxxxxxxxxxx>
CommitDate: Fri Mar 12 17:00:30 2021 +0000

    x86/AMD: expose HWCR.TscFreqSel to guests
    
    Linux has been warning ("firmware bug") about this bit being clear for a
    long time. While writable in older hardware it has been readonly on more
    than just most recent hardware. For simplicitly report it always set (if
    anything we may want to log the issue ourselves if it turns out to be
    clear on older hardware) on CPU families 10h and up (in family 0fh the
    bit is part of a larger field of different purpose).
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
    Acked-by: Ian Jackson <iwj@xxxxxxxxxxxxxx>
---
 xen/arch/x86/msr.c              | 7 +++++++
 xen/include/asm-x86/msr-index.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 8ed0b4e982..0ebcb04259 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -315,6 +315,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t 
*val)
         *val = msrs->tsc_aux;
         break;
 
+    case MSR_K8_HWCR:
+        if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+            goto gp_fault;
+        *val = get_cpu_family(cp->basic.raw_fms, NULL, NULL) >= 0x10
+               ? K8_HWCR_TSC_FREQ_SEL : 0;
+        break;
+
     case MSR_AMD64_DE_CFG:
         if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             goto gp_fault;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 1f5a5d0e38..f2e34dd22b 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -287,6 +287,8 @@
 
 #define MSR_K7_HWCR                    0xc0010015
 #define MSR_K8_HWCR                    0xc0010015
+#define K8_HWCR_TSC_FREQ_SEL           (1ULL << 24)
+
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K8_PSTATE_LIMIT            0xc0010061
--
generated by git-patchbot for /home/xen/git/xen.git#staging