[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging] x86/vpic: issue dpci EOI for cleared pins at ICW1
commit 2d494f2198d7909a394085d079475bb099d7afe7 Author: Roger Pau Monné <roger.pau@xxxxxxxxxx> AuthorDate: Tue Apr 20 11:36:09 2021 +0200 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Tue Apr 20 11:36:09 2021 +0200 x86/vpic: issue dpci EOI for cleared pins at ICW1 When pins are cleared from either ISR or IRR as part of the initialization sequence forward the clearing of those pins to the dpci EOI handler, as it is equivalent to an EOI. Not doing so can bring the interrupt controller state out of sync with the dpci handling logic, that expects a notification when a pin has been EOI'ed. Fixes: 7b3cb5e5416 ('IRQ injection changes for HVM PCI passthru.') Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx> --- xen/arch/x86/hvm/vpic.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/xen/arch/x86/hvm/vpic.c b/xen/arch/x86/hvm/vpic.c index 795a76768d..f465b7f997 100644 --- a/xen/arch/x86/hvm/vpic.c +++ b/xen/arch/x86/hvm/vpic.c @@ -197,6 +197,8 @@ static void vpic_ioport_write( { if ( val & 0x10 ) { + unsigned int pending = vpic->isr | (vpic->irr & ~vpic->elcr); + /* ICW1 */ /* Clear edge-sensing logic. */ vpic->irr &= vpic->elcr; @@ -220,6 +222,24 @@ static void vpic_ioport_write( } vpic->init_state = ((val & 3) << 2) | 1; + vpic_update_int_output(vpic); + vpic_unlock(vpic); + + /* + * Forward the EOI of any pending or in service interrupt that has + * been cleared from IRR or ISR, or else the dpci logic will get + * out of sync with the state of the interrupt controller. + */ + while ( pending ) + { + unsigned int pin = __scanbit(pending, 8); + + ASSERT(pin < 8); + hvm_dpci_eoi(current->domain, + hvm_isa_irq_to_gsi((addr >> 7) ? (pin | 8) : pin)); + __clear_bit(pin, &pending); + } + return; } else if ( val & 0x08 ) { -- generated by git-patchbot for /home/xen/git/xen.git#staging
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