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[xen master] xen/arm: Always access SCTLR_EL2 using READ/WRITE_SYSREG()

commit 25e5d0c412e0d7420f2aa7fdd71cc39d8ed6c528
Author:     Michal Orzel <michal.orzel@xxxxxxx>
AuthorDate: Wed May 5 09:43:05 2021 +0200
Commit:     Julien Grall <jgrall@xxxxxxxxxx>
CommitDate: Mon May 10 18:16:34 2021 +0100

    xen/arm: Always access SCTLR_EL2 using READ/WRITE_SYSREG()
    The Armv8 specification describes the system register as a 64-bit value
    on AArch64 and 32-bit value on AArch32 (same as ARMv7).
    Unfortunately, Xen is accessing the system registers using
    READ/WRITE_SYSREG32() which means the top 32-bit are clobbered.
    This is only a latent bug so far because Xen will not yet use the top
    There is also no change in behavior because arch/arm/arm64/head.S will
    initialize SCTLR_EL2 to a sane value with the top 32-bit zeroed.
    Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
    Acked-by: Julien Grall <jgrall@xxxxxxxxxx>
 xen/arch/arm/mm.c    | 2 +-
 xen/arch/arm/traps.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 59f8a3f15f..0e07335291 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -613,7 +613,7 @@ void __init remove_early_mappings(void)
 static void xen_pt_enforce_wnx(void)
      * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
      * before flushing the TLBs.
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index c7acdb2087..e7384381cc 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -915,7 +915,7 @@ static void _show_registers(const struct cpu_user_regs 
     printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2);
-    printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2));
+    printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2));
     printk("   HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2));
     printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2));
generated by git-patchbot for /home/xen/git/xen.git#master



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