[xen master] x86/AMD: also determine L3 cache size

[patchbot@xxxxxxx]

commit 12a963b22b02a377ddb6a46db304fa4a0eee8c39
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Mon May 17 15:40:53 2021 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon May 17 15:40:53 2021 +0200

    x86/AMD: also determine L3 cache size
    
    For Intel CPUs we record L3 cache size, hence we should also do so for
    AMD and alike.
    
    While making these additions, also make sure (throughout the function)
    that we don't needlessly overwrite prior values when the new value to be
    stored is zero.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/cpu/common.c | 39 ++++++++++++++++++++++++++-------------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 0eb364f8a6..302f7f35d8 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -240,28 +240,41 @@ int get_model_name(struct cpuinfo_x86 *c)
 
 void display_cacheinfo(struct cpuinfo_x86 *c)
 {
-       unsigned int dummy, ecx, edx, l2size;
+       unsigned int dummy, ecx, edx, size;
 
        if (c->extended_cpuid_level >= 0x80000005) {
                cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
-               if (opt_cpu_info)
-                       printk("CPU: L1 I cache %dK (%d bytes/line),"
-                                     " D cache %dK (%d bytes/line)\n",
-                              edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
-               c->x86_cache_size=(ecx>>24)+(edx>>24);  
+               if ((edx | ecx) >> 24) {
+                       if (opt_cpu_info)
+                               printk("CPU: L1 I cache %uK (%u bytes/line),"
+                                             " D cache %uK (%u bytes/line)\n",
+                                      edx >> 24, edx & 0xFF, ecx >> 24, ecx & 
0xFF);
+                       c->x86_cache_size = (ecx >> 24) + (edx >> 24);
+               }
        }
 
        if (c->extended_cpuid_level < 0x80000006)       /* Some chips just has 
a large L1. */
                return;
 
-       ecx = cpuid_ecx(0x80000006);
-       l2size = ecx >> 16;
-       
-       c->x86_cache_size = l2size;
+       cpuid(0x80000006, &dummy, &dummy, &ecx, &edx);
 
-       if (opt_cpu_info)
-               printk("CPU: L2 Cache: %dK (%d bytes/line)\n",
-                      l2size, ecx & 0xFF);
+       size = ecx >> 16;
+       if (size) {
+               c->x86_cache_size = size;
+
+               if (opt_cpu_info)
+                       printk("CPU: L2 Cache: %uK (%u bytes/line)\n",
+                              size, ecx & 0xFF);
+       }
+
+       size = edx >> 18;
+       if (size) {
+               c->x86_cache_size = size * 512;
+
+               if (opt_cpu_info)
+                       printk("CPU: L3 Cache: %uM (%u bytes/line)\n",
+                              (size + (size & 1)) >> 1, edx & 0xFF);
+       }
 }
 
 static inline u32 _phys_pkg_id(u32 cpuid_apic, int index_msb)
--
generated by git-patchbot for /home/xen/git/xen.git#master