[xen staging] From: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>

[patchbot@xxxxxxx]

commit dd8238a6114f186276293f401aa449aca991c029
Author:     Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>
AuthorDate: Mon Jan 24 08:43:44 2022 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Jan 24 08:43:44 2022 +0100

    From: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>
    x86/mwait-idle: add SnowRidge C-state table
    
    Add C-state table for the SnowRidge SoC which is found on Intel Jacobsville
    platforms.
    
    The following has been changed.
    
     1. C1E latency changed from 10us to 15us. It was measured using the
        open source "wult" tool (the "nic" method, 15us is the 99.99th
        percentile).
    
     2. C1E power break even changed from 20us to 25us, which may result
        in less C1E residency in some workloads.
    
     3. C6 latency changed from 50us to 130us. Measured the same way as C1E.
    
    The C6 C-state is supported only by some SnowRidge revisions, so add a 
C-state
    table commentary about this.
    
    On SnowRidge, C6 support is enumerated via the usual mechanism: "mwait" 
leaf of
    the "cpuid" instruction. The 'intel_idle' driver does check this leaf, so 
even
    though C6 is present in the table, the driver will only use it if the CPU 
does
    support it.
    
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
    [Linux commit: 9cf93f056f783f986c19f40d5304d1bcffa0fc0d]
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
 xen/arch/x86/cpu/mwait-idle.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 158741fc71..12524eefd4 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -742,6 +742,32 @@ static const struct cpuidle_state dnv_cstates[] = {
        {}
 };
 
+/*
+ * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
+ * C6, and this is indicated in the CPUID mwait leaf.
+ */
+static const struct cpuidle_state snr_cstates[] = {
+       {
+               .name = "C1",
+               .flags = MWAIT2flg(0x00),
+               .exit_latency = 2,
+               .target_residency = 2,
+       },
+       {
+               .name = "C1E",
+               .flags = MWAIT2flg(0x01),
+               .exit_latency = 15,
+               .target_residency = 25,
+       },
+       {
+               .name = "C6",
+               .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 130,
+               .target_residency = 500,
+       },
+       {}
+};
+
 static void mwait_idle(void)
 {
        unsigned int cpu = smp_processor_id();
@@ -954,6 +980,11 @@ static const struct idle_cpu idle_cpu_dnv = {
        .disable_promotion_to_c1e = true,
 };
 
+static const struct idle_cpu idle_cpu_snr = {
+       .state_table = snr_cstates,
+       .disable_promotion_to_c1e = true,
+};
+
 #define ICPU(model, cpu) \
        { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu}
 
@@ -996,7 +1027,7 @@ static const struct x86_cpu_id intel_idle_ids[] 
__initconstrel = {
        ICPU(0x5c, bxt),
        ICPU(0x7a, bxt),
        ICPU(0x5f, dnv),
-       ICPU(0x86, dnv),
+       ICPU(0x86, snr),
        {}
 };
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging