[xen staging] x86/Intel: IceLake D + Sapphire Rapids Xeons also support PPIN

[patchbot@xxxxxxx]

commit df6f5cd9e51e742b23dcee99907e97a435716061
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Thu Jan 27 13:50:19 2022 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Jan 27 13:50:19 2022 +0100

    x86/Intel: IceLake D + Sapphire Rapids Xeons also support PPIN
    
    This is as per Linux commits a331f5fdd36d ("x86/mce: Add Xeon Sapphire
    Rapids to list of CPUs that support PPIN") and [tip.git] e464121f2d40
    ("x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN"), just
    in case a subsequent change making use of the respective new CPUID bit
    doesn't cover either of these models.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c 
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index bb9f3a3ff7..d0161e9d4d 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -872,7 +872,9 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case 0x56: /* Broadwell Xeon D */
     case 0x57: /* Knights Landing */
     case 0x6a: /* Icelake X */
+    case 0x6c: /* Icelake D */
     case 0x85: /* Knights Mill */
+    case 0x8f: /* Sapphire Rapids X */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )
--
generated by git-patchbot for /home/xen/git/xen.git#staging