[xen staging] x86/cpuid: add CPUID flag for Extended Destination ID support

[patchbot@xxxxxxx]

commit f5592322062f7912dc45b30606f20691f6e1c3ee
Author:     Roger Pau Monné <roger.pau@xxxxxxxxxx>
AuthorDate: Fri Feb 18 09:17:47 2022 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Feb 18 09:17:47 2022 +0100

    x86/cpuid: add CPUID flag for Extended Destination ID support
    
    Introduce the CPUID flag to be used in order to signal the support for
    using an extended destination ID in IO-APIC RTEs and MSI address
    fields. Such format expands the maximum target APIC ID from 255 to
    32768 without requiring the usage of interrupt remapping.
    
    The design document describing the feature can be found at:
    
    http://david.woodhou.se/15-bit-msi.pdf
    
    Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/include/public/arch-x86/cpuid.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/include/public/arch-x86/cpuid.h 
b/xen/include/public/arch-x86/cpuid.h
index ce46305bee..f2b2b3632c 100644
--- a/xen/include/public/arch-x86/cpuid.h
+++ b/xen/include/public/arch-x86/cpuid.h
@@ -102,6 +102,13 @@
 #define XEN_HVM_CPUID_IOMMU_MAPPINGS   (1u << 2)
 #define XEN_HVM_CPUID_VCPU_ID_PRESENT  (1u << 3) /* vcpu id is present in EBX 
*/
 #define XEN_HVM_CPUID_DOMID_PRESENT    (1u << 4) /* domid is present in ECX */
+/*
+ * With interrupt format set to 0 (non-remappable) bits 55:49 from the
+ * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
+ * high bits for the Destination ID. This expands the Destination ID
+ * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
+ */
+#define XEN_HVM_CPUID_EXT_DEST_ID      (1u << 5)
 
 /*
  * Leaf 6 (0x40000x05)
--
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