[xen staging] x86/mwait-idle: add SPR support

[patchbot@xxxxxxx]

commit 9c432b876bf518866d431bda73f2be1250f688eb
Author:     Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>
AuthorDate: Thu Apr 28 10:00:18 2022 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Apr 28 10:00:18 2022 +0200

    x86/mwait-idle: add SPR support
    
    Add Sapphire Rapids Xeon support.
    
    Up until very recently, the C1 and C1E C-states were independent, but this
    has changed in some new chips, including Sapphire Rapids Xeon (SPR). In 
these
    chips the C1 and C1E states cannot be enabled at the same time. The "C1E
    promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit.
    
    Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR.
    
    1. If C1E promotion bit is disabled.
       a. C1  requests end up with C1  C-state.
       b. C1E requests end up with C1E C-state.
    2. If C1E promotion bit is enabled.
       a. C1  requests end up with C1E C-state.
       b. C1E requests end up with C1E C-state.
    
    Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon.
    1. If C1E promotion bit is disabled.
       a. C1  requests end up with C1 C-state.
       b. C1E requests end up with C1 C-state.
    2. If C1E promotion bit is enabled.
       a. C1  requests end up with C1E C-state.
       b. C1E requests end up with C1E C-state.
    
    Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was
    exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot 
be
    enabled at the same time.
    
    This patch adds both C1 and C1E states. However, C1E is marked as with the
    "CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by
    default. The C1E promotion bit will be cleared, which means that by default
    only C1 and C6 will be registered on SPR.
    
    The next patch will add an option for enabling C1E and disabling C1 on SPR.
    
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx>
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
    Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
9edf3c0ffef0
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
 xen/arch/x86/cpu/mwait-idle.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 99b9ad32f2..6add64dc5f 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -586,6 +586,38 @@ static const struct cpuidle_state icx_cstates[] = {
        {}
 };
 
+/*
+ * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vice
+ * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in
+ * MSR_IA32_POWER_CTL. But in this case there effectively no C1, because C1
+ * requests are promoted to C1E. If the "C1E promotion" bit is cleared, then
+ * both C1 and C1E requests end up with C1, so there is effectively no C1E.
+ *
+ * By default we enable C1 and disable C1E by marking it with
+ * 'CPUIDLE_FLAG_DISABLED'.
+ */
+static struct cpuidle_state __read_mostly spr_cstates[] = {
+       {
+               .name = "C1",
+               .flags = MWAIT2flg(0x00),
+               .exit_latency = 1,
+               .target_residency = 1,
+       },
+       {
+               .name = "C1E",
+               .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_DISABLED,
+               .exit_latency = 2,
+               .target_residency = 4,
+       },
+       {
+               .name = "C6",
+               .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 290,
+               .target_residency = 800,
+       },
+       {}
+};
+
 static const struct cpuidle_state atom_cstates[] = {
        {
                .name = "C1E",
@@ -972,6 +1004,11 @@ static const struct idle_cpu idle_cpu_icx = {
        .disable_promotion_to_c1e = true,
 };
 
+static struct idle_cpu __read_mostly idle_cpu_spr = {
+       .state_table = spr_cstates,
+       .disable_promotion_to_c1e = true,
+};
+
 static const struct idle_cpu idle_cpu_avn = {
        .state_table = avn_cstates,
        .disable_promotion_to_c1e = true,
@@ -1034,6 +1071,7 @@ static const struct x86_cpu_id intel_idle_ids[] 
__initconstrel = {
        ICPU(SKYLAKE_X,                 skx),
        ICPU(ICELAKE_X,                 icx),
        ICPU(ICELAKE_D,                 icx),
+       ICPU(SAPPHIRERAPIDS_X,          spr),
        ICPU(XEON_PHI_KNL,              knl),
        ICPU(XEON_PHI_KNM,              knl),
        ICPU(ATOM_GOLDMONT,             bxt),
--
generated by git-patchbot for /home/xen/git/xen.git#staging