[xen staging-4.15] x86/cpuid: Enumeration for BTC_NO

[patchbot@xxxxxxx]

commit 2b29ac476fa0c91655906fac3512202e514ecbed
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Mon May 16 15:48:24 2022 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Jul 12 16:28:26 2022 +0100

    x86/cpuid: Enumeration for BTC_NO
    
    BTC_NO indicates that hardware is not succeptable to Branch Type Confusion.
    
    Zen3 CPUs don't suffer BTC.
    
    This is part of XSA-407.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    (cherry picked from commit 76cb04ad64f3ab9ae785988c40655a71dde9c319)
---
 tools/libs/light/libxl_cpuid.c              |  1 +
 tools/misc/xen-cpuid.c                      |  2 +-
 xen/arch/x86/cpu/amd.c                      | 10 ++++++++++
 xen/arch/x86/spec_ctrl.c                    |  5 +++--
 xen/include/public/arch-x86/cpufeatureset.h |  1 +
 5 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index 9a4eb8015a..2632efc6ad 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -283,6 +283,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list 
*cpuid, const char* str)
         {"virt-ssbd",    0x80000008, NA, CPUID_REG_EBX, 25,  1},
         {"ssb-no",       0x80000008, NA, CPUID_REG_EBX, 26,  1},
         {"psfd",         0x80000008, NA, CPUID_REG_EBX, 28,  1},
+        {"btc-no",       0x80000008, NA, CPUID_REG_EBX, 29,  1},
 
         {"nc",           0x80000008, NA, CPUID_REG_ECX,  0,  8},
         {"apicidsize",   0x80000008, NA, CPUID_REG_ECX, 12,  4},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 12111fe12d..e83bc4793d 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -157,7 +157,7 @@ static const char *const str_e8b[32] =
     /* [22] */                 [23] = "ppin",
     [24] = "amd-ssbd",         [25] = "virt-ssbd",
     [26] = "ssb-no",
-    [28] = "psfd",
+    [28] = "psfd",             [29] = "btc-no",
 };
 
 static const char *const str_7d0[32] =
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 986672a072..675b877f19 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -822,6 +822,16 @@ static void init_amd(struct cpuinfo_x86 *c)
                        warning_add(text);
                }
                break;
+
+       case 0x19:
+               /*
+                * Zen3 (Fam19h model < 0x10) parts are not susceptible to
+                * Branch Type Confusion, but predate the allocation of the
+                * BTC_NO bit.  Fill it back in if we're not virtualised.
+                */
+               if (!cpu_has_hypervisor && !cpu_has(c, X86_FEATURE_BTC_NO))
+                       __set_bit(X86_FEATURE_BTC_NO, c->x86_capability);
+               break;
        }
 
        display_cacheinfo(c);
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index ced0f8c2ae..9f66c71551 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -388,7 +388,7 @@ static void __init print_details(enum ind_thunk thunk, 
uint64_t caps)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"      
  : "",
            (caps & ARCH_CAPS_IBRS_ALL)                       ? " IBRS_ALL"     
  : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"         
  : "",
@@ -403,7 +403,8 @@ static void __init print_details(enum ind_thunk thunk, 
uint64_t caps)
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS_ALWAYS))    ? " IBRS_ALWAYS"  
  : "",
            (e8b  & cpufeat_mask(X86_FEATURE_STIBP_ALWAYS))   ? " STIBP_ALWAYS" 
  : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS_FAST))      ? " IBRS_FAST"    
  : "",
-           (e8b  & cpufeat_mask(X86_FEATURE_IBRS_SAME_MODE)) ? " 
IBRS_SAME_MODE" : "");
+           (e8b  & cpufeat_mask(X86_FEATURE_IBRS_SAME_MODE)) ? " 
IBRS_SAME_MODE" : "",
+           (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"       
  : "");
 
     /* Hardware features which need driving to mitigate issues. */
     printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s\n",
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 9686c82ed7..1bbc7da4b5 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -265,6 +265,7 @@ XEN_CPUFEATURE(AMD_SSBD,      8*32+24) /*S  
MSR_SPEC_CTRL.SSBD available */
 XEN_CPUFEATURE(VIRT_SSBD,     8*32+25) /*   MSR_VIRT_SPEC_CTRL.SSBD */
 XEN_CPUFEATURE(SSB_NO,        8*32+26) /*A  Hardware not vulnerable to SSB */
 XEN_CPUFEATURE(PSFD,          8*32+28) /*S  MSR_SPEC_CTRL.PSFD */
+XEN_CPUFEATURE(BTC_NO,        8*32+29) /*A  Hardware not vulnerable to Branch 
Type Confusion */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
 XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A  AVX512 Neural Network Instructions 
*/
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.15