[xen staging-4.14] x86/spec-ctrl: Enable Zen2 chickenbit

[patchbot@xxxxxxx]

commit 5bccfbb68d7ac8709deb6671e5c87bb96e200c58
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Mar 15 18:30:25 2022 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Jul 12 16:31:49 2022 +0100

    x86/spec-ctrl: Enable Zen2 chickenbit
    
    ... as instructed in the Branch Type Confusion whitepaper.
    
    This is part of XSA-407.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    (cherry picked from commit 9deaf2d932f08c16c6b96a1c426e4b1142c0cdbe)
---
 xen/arch/x86/cpu/amd.c          | 28 ++++++++++++++++++++++++++++
 xen/arch/x86/cpu/cpu.h          |  1 +
 xen/arch/x86/cpu/hygon.c        |  6 ++++++
 xen/include/asm-x86/msr-index.h |  1 +
 4 files changed, 36 insertions(+)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 7409af98f6..f50f91f81e 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -731,6 +731,31 @@ void amd_init_ssbd(const struct cpuinfo_x86 *c)
                printk_once(XENLOG_ERR "No SSBD controls available\n");
 }
 
+/*
+ * On Zen2 we offer this chicken (bit) on the altar of Speculation.
+ *
+ * Refer to the AMD Branch Type Confusion whitepaper:
+ * https://XXX
+ *
+ * Setting this unnamed bit supposedly causes prediction information on
+ * non-branch instructions to be ignored.  It is to be set unilaterally in
+ * newer microcode.
+ *
+ * This chickenbit is something unrelated on Zen1, and Zen1 vs Zen2 isn't a
+ * simple model number comparison, so use STIBP as a heuristic to separate the
+ * two uarches in Fam17h(AMD)/18h(Hygon).
+ */
+void amd_init_spectral_chicken(void)
+{
+       uint64_t val, chickenbit = 1 << 1;
+
+       if (cpu_has_hypervisor || !boot_cpu_has(X86_FEATURE_AMD_STIBP))
+               return;
+
+       if (rdmsr_safe(MSR_AMD64_DE_CFG2, val) == 0 && !(val & chickenbit))
+               wrmsr_safe(MSR_AMD64_DE_CFG2, val | chickenbit);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
        u32 l, h;
@@ -783,6 +808,9 @@ static void init_amd(struct cpuinfo_x86 *c)
 
        amd_init_ssbd(c);
 
+       if (c->x86 == 0x17)
+               amd_init_spectral_chicken();
+
        /* MFENCE stops RDTSC speculation */
        if (!cpu_has_lfence_dispatch)
                __set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 1a5b3918b3..e76ab5ce1a 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -22,3 +22,4 @@ void early_init_amd(struct cpuinfo_x86 *c);
 void amd_log_freq(const struct cpuinfo_x86 *c);
 void amd_init_lfence(struct cpuinfo_x86 *c);
 void amd_init_ssbd(const struct cpuinfo_x86 *c);
+void amd_init_spectral_chicken(void);
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 3845e0cf0e..0cb0e7d55e 100644
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -36,6 +36,12 @@ static void init_hygon(struct cpuinfo_x86 *c)
 
        amd_init_ssbd(c);
 
+       /*
+        * TODO: Check heuristic safety with Hygon first
+       if (c->x86 == 0x18)
+               amd_init_spectral_chicken();
+        */
+
        /* MFENCE stops RDTSC speculation */
        if (!cpu_has_lfence_dispatch)
                __set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index c8670eab8e..4c1cba589d 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -359,6 +359,7 @@
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_DE_CFG               0xc0011029
 #define AMD64_DE_CFG_LFENCE_SERIALISE  (_AC(1, ULL) << 1)
+#define MSR_AMD64_DE_CFG2              0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK     0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK     0xc0011019
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.14