[xen staging-4.16] xen/arm: head: Add missing isb after writing to SCTLR_EL2/HSCTLR

[patchbot@xxxxxxx]

commit 0d362e5ed3fa1b307834bcffbf7fd5341e32ebfd
Author:     Julien Grall <jgrall@xxxxxxxxxx>
AuthorDate: Sat Jul 16 15:34:07 2022 +0100
Commit:     Stefano Stabellini <stefano.stabellini@xxxxxxx>
CommitDate: Wed Aug 3 14:57:53 2022 -0700

    xen/arm: head: Add missing isb after writing to SCTLR_EL2/HSCTLR
    
    Write to SCTLR_EL2/HSCTLR may not be visible until the next context
    synchronization. When initializing the CPU, we want the update to take
    effect right now. So add an isb afterwards.
    
    Spec references:
        - AArch64: D13.1.2 ARM DDI 0406C.d
        - AArch32 v8: G8.1.2 ARM DDI 0406C.d
        - AArch32 v7: B5.6.3 ARM DDI 0406C.d
    
    Signed-off-by: Julien Grall <jgrall@xxxxxxxxxx>
    Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>
    (cherry picked from commit 25424d1a6b7b7e875230aba77c2f044a4883e49a)
---
 xen/arch/arm/arm32/head.S | 1 +
 xen/arch/arm/arm64/head.S | 1 +
 2 files changed, 2 insertions(+)

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 7178865f48..854481f4f9 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -353,6 +353,7 @@ cpu_init_done:
 
         ldr   r0, =HSCTLR_SET
         mcr   CP32(r0, HSCTLR)
+        isb
 
         mov   pc, r5                        /* Return address is in r5 */
 ENDPROC(cpu_init)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 057dd5d925..42a2177c53 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -485,6 +485,7 @@ cpu_init:
 
         ldr   x0, =SCTLR_EL2_SET
         msr   SCTLR_EL2, x0
+        isb
 
         /*
          * Ensure that any exceptions encountered at EL2
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.16