|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging] x86/mwait-idle: add AlderLake support
commit 0fa9c3ef1e9196e8cd38c1532d29cf670dc21bcb
Author: Zhang Rui <rui.zhang@xxxxxxxxx>
AuthorDate: Thu Oct 13 17:54:23 2022 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Oct 13 17:54:23 2022 +0200
x86/mwait-idle: add AlderLake support
Similar to SPR, the C1 and C1E states on ADL are mutually exclusive.
Only one of them can be enabled at a time.
But contrast to SPR, which usually has a strong latency requirement
as a Xeon processor, C1E is preferred on ADL for better energy
efficiency.
Add custom C-state tables for ADL with both C1 and C1E, and
1. Enable the "C1E promotion" bit in MSR_IA32_POWER_CTL and mark C1
with the CPUIDLE_FLAG_UNUSABLE flag, so C1 is not available by
default.
2. Add support for the "preferred_cstates" module parameter, so that
users can choose to use C1 instead of C1E by booting with
"intel_idle.preferred_cstates=2".
Separate custom C-state tables are introduced for the ADL mobile and
desktop processors, because of the exit latency differences between
these two variants, especially with respect to PC10.
Signed-off-by: Zhang Rui <rui.zhang@xxxxxxxxx>
[ rjw: Changelog edits, code rearrangement ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
d1cf8bbfed1e
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx>
---
xen/arch/x86/cpu/mwait-idle.c | 116 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 17d756881a..86c47a04c7 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -605,6 +605,84 @@ static const struct cpuidle_state icx_cstates[] = {
{}
};
+/*
+ * On AlderLake C1 has to be disabled if C1E is enabled, and vice versa.
+ * C1E is enabled only if "C1E promotion" bit is set in MSR_IA32_POWER_CTL.
+ * But in this case there is effectively no C1, because C1 requests are
+ * promoted to C1E. If the "C1E promotion" bit is cleared, then both C1
+ * and C1E requests end up with C1, so there is effectively no C1E.
+ *
+ * By default we enable C1E and disable C1 by marking it with
+ * 'CPUIDLE_FLAG_DISABLED'.
+ */
+static struct cpuidle_state __read_mostly adl_cstates[] = {
+ {
+ .name = "C1",
+ .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_DISABLED,
+ .exit_latency = 1,
+ .target_residency = 1,
+ },
+ {
+ .name = "C1E",
+ .flags = MWAIT2flg(0x01),
+ .exit_latency = 2,
+ .target_residency = 4,
+ },
+ {
+ .name = "C6",
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 220,
+ .target_residency = 600,
+ },
+ {
+ .name = "C8",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 280,
+ .target_residency = 800,
+ },
+ {
+ .name = "C10",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 680,
+ .target_residency = 2000,
+ },
+ {}
+};
+
+static struct cpuidle_state __read_mostly adl_l_cstates[] = {
+ {
+ .name = "C1",
+ .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_DISABLED,
+ .exit_latency = 1,
+ .target_residency = 1,
+ },
+ {
+ .name = "C1E",
+ .flags = MWAIT2flg(0x01),
+ .exit_latency = 2,
+ .target_residency = 4,
+ },
+ {
+ .name = "C6",
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 170,
+ .target_residency = 500,
+ },
+ {
+ .name = "C8",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 200,
+ .target_residency = 600,
+ },
+ {
+ .name = "C10",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 230,
+ .target_residency = 700,
+ },
+ {}
+};
+
/*
* On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vice
* versa. On SPR C1E is enabled only if "C1E promotion" bit is set in
@@ -1032,6 +1110,14 @@ static const struct idle_cpu idle_cpu_icx = {
.c1e_promotion = C1E_PROMOTION_DISABLE,
};
+static struct idle_cpu __read_mostly idle_cpu_adl = {
+ .state_table = adl_cstates,
+};
+
+static struct idle_cpu __read_mostly idle_cpu_adl_l = {
+ .state_table = adl_l_cstates,
+};
+
static struct idle_cpu __read_mostly idle_cpu_spr = {
.state_table = spr_cstates,
.c1e_promotion = C1E_PROMOTION_DISABLE,
@@ -1099,6 +1185,8 @@ static const struct x86_cpu_id intel_idle_ids[]
__initconstrel = {
ICPU(SKYLAKE_X, skx),
ICPU(ICELAKE_X, icx),
ICPU(ICELAKE_D, icx),
+ ICPU(ALDERLAKE, adl),
+ ICPU(ALDERLAKE_L, adl_l),
ICPU(SAPPHIRERAPIDS_X, spr),
ICPU(XEON_PHI_KNL, knl),
ICPU(XEON_PHI_KNM, knl),
@@ -1268,6 +1356,30 @@ static void __init skx_idle_state_table_update(void)
}
}
+/*
+ * adl_idle_state_table_update - Adjust AlderLake idle states table.
+ */
+static void __init adl_idle_state_table_update(void)
+{
+ /* Check if user prefers C1 over C1E. */
+ if ((preferred_states_mask & BIT(1, U)) &&
+ !(preferred_states_mask & BIT(2, U))) {
+ adl_cstates[0].flags &= ~CPUIDLE_FLAG_DISABLED;
+ adl_cstates[1].flags |= CPUIDLE_FLAG_DISABLED;
+ adl_l_cstates[0].flags &= ~CPUIDLE_FLAG_DISABLED;
+ adl_l_cstates[1].flags |= CPUIDLE_FLAG_DISABLED;
+
+ /* Disable C1E by clearing the "C1E promotion" bit. */
+ idle_cpu_adl.c1e_promotion = C1E_PROMOTION_DISABLE;
+ idle_cpu_adl_l.c1e_promotion = C1E_PROMOTION_DISABLE;
+ return;
+ }
+
+ /* Make sure C1E is enabled by default */
+ idle_cpu_adl.c1e_promotion = C1E_PROMOTION_ENABLE;
+ idle_cpu_adl_l.c1e_promotion = C1E_PROMOTION_ENABLE;
+}
+
/*
* spr_idle_state_table_update - Adjust Sapphire Rapids idle states table.
*/
@@ -1324,6 +1436,10 @@ static void __init mwait_idle_state_table_update(void)
case INTEL_FAM6_SAPPHIRERAPIDS_X:
spr_idle_state_table_update();
break;
+ case INTEL_FAM6_ALDERLAKE:
+ case INTEL_FAM6_ALDERLAKE_L:
+ adl_idle_state_table_update();
+ break;
}
}
--
generated by git-patchbot for /home/xen/git/xen.git#staging
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |