[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86/mwait-idle: add core C6 optimization for SPR
commit 13ecd1c216433125836c0516219a0854640eeeed Author: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx> AuthorDate: Thu Oct 13 17:53:26 2022 +0200 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Thu Oct 13 17:53:26 2022 +0200 x86/mwait-idle: add core C6 optimization for SPR From: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx> Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to match core C6 values, instead of using the default package C6 values. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3a9cf77b60dc Make sure a contradictory "preferred-cstates" wouldn't cause bypassing of the added logic. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx> --- xen/arch/x86/cpu/mwait-idle.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index cc62ddf743..17d756881a 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1273,18 +1273,31 @@ static void __init skx_idle_state_table_update(void) */ static void __init spr_idle_state_table_update(void) { - /* Check if user prefers C1E over C1. */ - if (preferred_states_mask & BIT(2, U)) { - if (preferred_states_mask & BIT(1, U)) - /* Both can't be enabled, stick to the defaults. */ - return; + uint64_t msr; + /* Check if user prefers C1E over C1. */ + if ((preferred_states_mask & BIT(2, U)) && + !(preferred_states_mask & BIT(1, U))) { + /* Disable C1 and enable C1E. */ spr_cstates[0].flags |= CPUIDLE_FLAG_DISABLED; spr_cstates[1].flags &= ~CPUIDLE_FLAG_DISABLED; /* Request enabling C1E using the "C1E promotion" bit. */ idle_cpu_spr.c1e_promotion = C1E_PROMOTION_ENABLE; } + + /* + * By default, the C6 state assumes the worst-case scenario of package + * C6. However, if PC6 is disabled, we update the numbers to match + * core C6. + */ + rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* Limit value 2 and above allow for PC6. */ + if ((msr & 0x7) < 2) { + spr_cstates[2].exit_latency = 190; + spr_cstates[2].target_residency = 600; + } } /* -- generated by git-patchbot for /home/xen/git/xen.git#master
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