[xen master] xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by VA

[patchbot@xxxxxxx]

commit cbfaf6ccd2cb5d1b2bc6efe5c6f4ba5cccce5689
Author:     Julien Grall <jgrall@xxxxxxxxxx>
AuthorDate: Tue Jan 24 19:25:50 2023 +0000
Commit:     Julien Grall <jgrall@xxxxxxxxxx>
CommitDate: Tue Jan 24 19:34:44 2023 +0000

    xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by 
VA
    
    Looking at the Neoverse N1 errata document, it is not clear to me
    why the TLBI repeat workaround is not applied for TLB flush by VA.
    
    The TLB flush by VA helpers are used in flush_xen_tlb_range_va_local()
    and flush_xen_tlb_range_va(). So if the range size is a fixed size smaller
    than a PAGE_SIZE, it would be possible that the compiler remove the loop
    and therefore replicate the sequence described in the erratum 1286807.
    
    So the TLBI repeat workaround should also be applied for the TLB flush
    by VA helpers.
    
    Fixes: 22e323d115d8 ("xen/arm: Add workaround for Cortex-A76/Neoverse-N1 
erratum #1286807")
    Signed-off-by: Julien Grall <jgrall@xxxxxxxxxx>
    Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
    Tested-by: Henry Wang <Henry.Wang@xxxxxxx>
---
 xen/arch/arm/include/asm/arm64/flushtlb.h | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h 
b/xen/arch/arm/include/asm/arm64/flushtlb.h
index 001ae4d1c3..3a9092b814 100644
--- a/xen/arch/arm/include/asm/arm64/flushtlb.h
+++ b/xen/arch/arm/include/asm/arm64/flushtlb.h
@@ -45,6 +45,27 @@ static inline void name(void)                    \
         : : : "memory");                         \
 }
 
+/*
+ * FLush TLB by VA. This will likely be used in a loop, so the caller
+ * is responsible to use the appropriate memory barriers before/after
+ * the sequence.
+ *
+ * See above about the ARM64_WORKAROUND_REPEAT_TLBI sequence.
+ */
+#define TLB_HELPER_VA(name, tlbop)               \
+static inline void name(vaddr_t va)              \
+{                                                \
+    asm volatile(                                \
+        "tlbi "  # tlbop  ", %0;"                \
+        ALTERNATIVE(                             \
+            "nop; nop;",                         \
+            "dsb  ish;"                          \
+            "tlbi "  # tlbop  ", %0;",           \
+            ARM64_WORKAROUND_REPEAT_TLBI,        \
+            CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \
+        : : "r" (va >> PAGE_SHIFT) : "memory");  \
+}
+
 /* Flush local TLBs, current VMID only. */
 TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh);
 
@@ -61,16 +82,10 @@ TLB_HELPER(flush_all_guests_tlb, alle1is, ish);
 TLB_HELPER(flush_xen_tlb_local, alle2, nsh);
 
 /* Flush TLB of local processor for address va. */
-static inline void  __flush_xen_tlb_one_local(vaddr_t va)
-{
-    asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
+TLB_HELPER_VA(__flush_xen_tlb_one_local, vae2);
 
 /* Flush TLB of all processors in the inner-shareable domain for address va. */
-static inline void __flush_xen_tlb_one(vaddr_t va)
-{
-    asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
+TLB_HELPER_VA(__flush_xen_tlb_one, vae2is);
 
 #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */
 /*
--
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