|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86emul: support AVX-VNNI-INT8
commit 842acaa743a503726d6c4d77a7982cc64f07c4bf
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Mon Apr 17 18:11:06 2023 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Apr 17 18:11:06 2023 +0200
x86emul: support AVX-VNNI-INT8
These are close relatives of the AVX-VNNI ISA extension. Since the insns
here and in particular their memory access patterns follow the usual
scheme (and especially the byte variants of AVX-VNNI), I didn't think it
was necessary to add a contrived test specifically for them.
While making the addition also re-wire AVX-VNNI's handling to
simd_0f_ymm: There's no reason to check the AVX feature alongside the
one actually of interest (there are a few features where two checks are
actually necessary, e.g. GFNI+AVX, but this isn't the case here).
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c | 2 ++
tools/tests/x86_emulator/predicates.c | 6 ++++++
tools/tests/x86_emulator/x86-emulate.h | 1 +
xen/arch/x86/include/asm/cpufeature.h | 3 +++
xen/arch/x86/x86_emulate/private.h | 1 +
xen/arch/x86/x86_emulate/x86_emulate.c | 12 +++++++++++-
xen/include/public/arch-x86/cpufeatureset.h | 1 +
xen/tools/gen-cpuid.py | 2 +-
9 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index 753345cc30..4f58f45ea0 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -238,6 +238,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
*cpuid, const char* str)
{"wrmsrns", 0x00000007, 1, CPUID_REG_EAX, 19, 1},
{"avx-ifma", 0x00000007, 1, CPUID_REG_EAX, 23, 1},
+ {"avx-vnni-int8",0x00000007, 1, CPUID_REG_EDX, 4, 1},
{"cet-sss", 0x00000007, 1, CPUID_REG_EDX, 18, 1},
{"intel-psfd", 0x00000007, 2, CPUID_REG_EDX, 0, 1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 76a3f6e840..ff22aec569 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -212,6 +212,8 @@ static const char *const str_7c1[32] =
static const char *const str_7d1[32] =
{
+ [ 4] = "avx-vnni-int8",
+
[18] = "cet-sss",
};
diff --git a/tools/tests/x86_emulator/predicates.c
b/tools/tests/x86_emulator/predicates.c
index eb493ddc49..bdaba65048 100644
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1336,8 +1336,14 @@ static const struct vex {
{ { 0x45 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsrlv{d,q} */
{ { 0x46 }, 2, T, R, pfx_66, W0, Ln }, /* vpsravd */
{ { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */
+ { { 0x50 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuud */
{ { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */
+ { { 0x50 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsud */
+ { { 0x50 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssd */
+ { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuuds */
{ { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */
+ { { 0x51 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsuds */
+ { { 0x51 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssds */
{ { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */
{ { 0x53 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssds */
{ { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastd */
diff --git a/tools/tests/x86_emulator/x86-emulate.h
b/tools/tests/x86_emulator/x86-emulate.h
index 78808783fd..fdb4766205 100644
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -186,6 +186,7 @@ void wrpkru(unsigned int val);
#define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6))
#define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6))
#define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6))
+#define cpu_has_avx_vnni_int8 (cp.feat.avx_vnni_int8 && xcr0_mask(6))
#define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1)
diff --git a/xen/arch/x86/include/asm/cpufeature.h
b/xen/arch/x86/include/asm/cpufeature.h
index e1353485ea..b7740f79bf 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -172,6 +172,9 @@ extern struct cpuinfo_x86 boot_cpu_data;
#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
#define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA)
+/* CPUID level 0x00000007:1.edx */
+#define cpu_has_avx_vnni_int8 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT8)
+
/* Synthesized. */
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
#define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
diff --git a/xen/arch/x86/x86_emulate/private.h
b/xen/arch/x86/x86_emulate/private.h
index ca03458e04..eff03481b8 100644
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -585,6 +585,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
#define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns)
#define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma)
+#define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8)
#define vcpu_must_have(feat) \
generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD)
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c
b/xen/arch/x86/x86_emulate/x86_emulate.c
index 9ac904dd1a..e049d6bb99 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6020,13 +6020,23 @@ x86_emulate(
generate_exception_if(vex.l, X86_EXC_UD);
goto simd_0f_avx;
+ case X86EMUL_OPC_VEX (0x0f38, 0x50): /* vpdpbuud
[xy]mm/mem,[xy]mm,[xy]mm */
+ case X86EMUL_OPC_VEX_F3(0x0f38, 0x50): /* vpdpbsud
[xy]mm/mem,[xy]mm,[xy]mm */
+ case X86EMUL_OPC_VEX_F2(0x0f38, 0x50): /* vpdpbssd
[xy]mm/mem,[xy]mm,[xy]mm */
+ case X86EMUL_OPC_VEX (0x0f38, 0x51): /* vpdpbuuds
[xy]mm/mem,[xy]mm,[xy]mm */
+ case X86EMUL_OPC_VEX_F3(0x0f38, 0x51): /* vpdpbsuds
[xy]mm/mem,[xy]mm,[xy]mm */
+ case X86EMUL_OPC_VEX_F2(0x0f38, 0x51): /* vpdpbssds
[xy]mm/mem,[xy]mm,[xy]mm */
+ host_and_vcpu_must_have(avx_vnni_int8);
+ generate_exception_if(vex.w, X86_EXC_UD);
+ goto simd_0f_ymm;
+
case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd
[xy]mm/mem,[xy]mm,[xy]mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds
[xy]mm/mem,[xy]mm,[xy]mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd
[xy]mm/mem,[xy]mm,[xy]mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0x53): /* vpdpwssds
[xy]mm/mem,[xy]mm,[xy]mm */
host_and_vcpu_must_have(avx_vnni);
generate_exception_if(vex.w, X86_EXC_UD);
- goto simd_0f_avx;
+ goto simd_0f_ymm;
case X86EMUL_OPC_EVEX_66(0x0f38, 0x50): /* vpdpbusd
[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x51): /* vpdpbusds
[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 24db511916..fc5e3ad1e8 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -302,6 +302,7 @@ XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */
/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
/* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
+XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructions */
XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks
safe to use */
#endif /* XEN_CPUFEATURE */
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 46e23a2fad..d77b38afa9 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -254,7 +254,7 @@ def crunch_numbers(state):
# feature flags. If want to use AVX512, AVX2 must be supported and
# enabled. Certain later extensions, acting on 256-bit vectors of
# integers, better depend on AVX2 than AVX.
- AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA],
+ AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8],
# AVX512F is taken to mean hardware support for 512bit registers
# (which in practice depends on the EVEX prefix to encode) as well
--
generated by git-patchbot for /home/xen/git/xen.git#master
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |