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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set
commit 7c3616e6f1aa541884410c6430e3c8986cf0973c
Author: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
AuthorDate: Wed Aug 30 16:53:26 2023 +0100
Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Wed Oct 18 16:03:33 2023 +0100
x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set
If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to
perform microcode updates. This is controlled through the DIS_MCU_LOAD bit
and is intended for baremetal clouds where the owner may not trust the
tenant to choose the microcode version in use. If we notice that bit being
set then simply disable the "apply_microcode" handler so we can't even try
to perform update (as it's known to be silently dropped).
While at it, remove the Intel family check, as microcode loading is
supported on every Intel64 CPU.
Signed-off-by: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx>
---
xen/arch/x86/cpu/microcode/core.c | 20 ++++++++++++++------
xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++++++
xen/arch/x86/cpu/microcode/private.h | 7 +++++++
xen/arch/x86/include/asm/cpufeature.h | 1 +
xen/arch/x86/include/asm/msr-index.h | 5 +++++
5 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/cpu/microcode/core.c
b/xen/arch/x86/cpu/microcode/core.c
index b3df4d40e6..65ebeb50de 100644
--- a/xen/arch/x86/cpu/microcode/core.c
+++ b/xen/arch/x86/cpu/microcode/core.c
@@ -847,17 +847,21 @@ int __init early_microcode_init(unsigned long *module_map,
{
const struct cpuinfo_x86 *c = &boot_cpu_data;
int rc = 0;
+ bool can_load = false;
switch ( c->x86_vendor )
{
case X86_VENDOR_AMD:
if ( c->x86 >= 0x10 )
+ {
ucode_ops = amd_ucode_ops;
+ can_load = true;
+ }
break;
case X86_VENDOR_INTEL:
- if ( c->x86 >= 6 )
- ucode_ops = intel_ucode_ops;
+ ucode_ops = intel_ucode_ops;
+ can_load = intel_can_load_microcode();
break;
}
@@ -871,13 +875,17 @@ int __init early_microcode_init(unsigned long *module_map,
/*
* Some hypervisors deliberately report a microcode revision of -1 to
- * mean that they will not accept microcode updates. We take the hint
- * and ignore the microcode interface in that case.
+ * mean that they will not accept microcode updates.
+ *
+ * It's also possible the hardware might have built-in support to disable
+ * updates and someone (e.g: a baremetal cloud provider) disabled them.
+ *
+ * Take the hint in either case and ignore the microcode interface.
*/
- if ( this_cpu(cpu_sig).rev == ~0 )
+ if ( this_cpu(cpu_sig).rev == ~0 || !can_load )
{
printk(XENLOG_INFO "Microcode loading disabled due to: %s\n",
- "rev = ~0");
+ can_load ? "rev = ~0" : "HW toggle");
ucode_ops.apply_microcode = NULL;
return -ENODEV;
}
diff --git a/xen/arch/x86/cpu/microcode/intel.c
b/xen/arch/x86/cpu/microcode/intel.c
index 8d4d6574aa..060c529a6e 100644
--- a/xen/arch/x86/cpu/microcode/intel.c
+++ b/xen/arch/x86/cpu/microcode/intel.c
@@ -385,6 +385,19 @@ static struct microcode_patch *cf_check
cpu_request_microcode(
return patch;
}
+bool __init intel_can_load_microcode(void)
+{
+ uint64_t mcu_ctrl;
+
+ if ( !cpu_has_mcu_ctrl )
+ return true;
+
+ rdmsrl(MSR_MCU_CONTROL, mcu_ctrl);
+
+ /* If DIS_MCU_LOAD is set applying microcode updates won't work */
+ return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD);
+}
+
const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = {
.cpu_request_microcode = cpu_request_microcode,
.collect_cpu_info = collect_cpu_info,
diff --git a/xen/arch/x86/cpu/microcode/private.h
b/xen/arch/x86/cpu/microcode/private.h
index 626aeb4d08..d80787205a 100644
--- a/xen/arch/x86/cpu/microcode/private.h
+++ b/xen/arch/x86/cpu/microcode/private.h
@@ -60,6 +60,13 @@ struct microcode_ops {
const struct microcode_patch *new, const struct microcode_patch *old);
};
+/**
+ * Checks whether we can perform microcode updates on this Intel system
+ *
+ * @return True iff the microcode update facilities are enabled
+ */
+bool intel_can_load_microcode(void);
+
extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops;
#endif /* ASM_X86_MICROCODE_PRIVATE_H */
diff --git a/xen/arch/x86/include/asm/cpufeature.h
b/xen/arch/x86/include/asm/cpufeature.h
index 0825343945..213c184b1c 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -201,6 +201,7 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO)
#define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL)
#define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO)
+#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL)
#define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR)
#define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA)
#define cpu_has_gds_ctrl boot_cpu_has(X86_FEATURE_GDS_CTRL)
diff --git a/xen/arch/x86/include/asm/msr-index.h
b/xen/arch/x86/include/asm/msr-index.h
index 7b3490bfb1..82a81bd0a2 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -183,6 +183,11 @@
#define MSR_PM_CTL1 0x00000db1
#define PM_CTL1_HDC_ALLOW_BLOCK BIT(0, ULL)
+#define MSR_MCU_CONTROL 0x00001406
+#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0)
+#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1)
+#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2)
+
#define MSR_UARCH_MISC_CTRL 0x00001b01
#define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
--
generated by git-patchbot for /home/xen/git/xen.git#master
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