[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] xen/arm: gicv3: clean up GICD_CTRL write
commit 1e2b13bcf0370eed53ece6f224a11651edb1f22e Author: Stewart Hildebrand <stewart.hildebrand@xxxxxxx> AuthorDate: Wed Nov 22 09:46:00 2023 -0500 Commit: Julien Grall <jgrall@xxxxxxxxxx> CommitDate: Thu Nov 23 10:54:02 2023 +0000 xen/arm: gicv3: clean up GICD_CTRL write GICD_CTL_ENABLE is a GICv2 bit. Remove it. The definitions of GICD_CTL_ENABLE and GICD_CTLR_ENABLE_G1 are identical, so the value written is unchanged. Signed-off-by: Stewart Hildebrand <stewart.hildebrand@xxxxxxx> Reviewed-by: Julien Grall <jgrall@xxxxxxxxxx> --- xen/arch/arm/gic-v3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 172ff8c005..9b35a8c8a7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -633,8 +633,8 @@ static void __init gicv3_dist_init(void) gicv3_dist_wait_for_rwp(); /* Turn on the distributor */ - writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS | - GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR); + writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | + GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR); /* Route all global IRQs to this CPU */ affinity = gicv3_mpidr_to_affinity(smp_processor_id()); -- generated by git-patchbot for /home/xen/git/xen.git#master
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