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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86/APIC: purge {GET,SET}_APIC_DELIVERY_MODE()
commit 439676165432ca687c3194701d0b014f1d67b9bb
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Mon Jan 29 09:22:35 2024 +0100
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Jan 29 09:22:35 2024 +0100
x86/APIC: purge {GET,SET}_APIC_DELIVERY_MODE()
The few uses we have can easily be replaced, eliminating the need for
redundant APIC_DM_* and APIC_MODE_* constants. Therefore also purge all
respective APIC_MODE_* constants, introducing APIC_DM_MASK anew instead.
This is further relevant since we have a different set of APIC_MODE_*,
which could otherwise end up confusing.
No functional change intended.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
xen/arch/x86/apic.c | 10 ++++------
xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ++--
xen/arch/x86/cpu/vpmu.c | 6 +++---
xen/arch/x86/hvm/vlapic.c | 18 +++++++++---------
xen/arch/x86/include/asm/apicdef.h | 7 +------
xen/arch/x86/oprofile/nmi_int.c | 2 +-
6 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index da41d2dfed..a69ac90405 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -263,22 +263,20 @@ void disconnect_bsp_APIC(int virt_wire_setup)
if (!virt_wire_setup) {
/* For LVT0 make it edge triggered, active high, external and
enabled */
value = apic_read(APIC_LVT0);
- value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+ value &= ~(APIC_DM_MASK | APIC_SEND_PENDING |
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
- value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
- value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+ value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING | APIC_DM_EXTINT;
apic_write(APIC_LVT0, value);
}
/* For LVT1 make it edge triggered, active high, nmi and enabled */
value = apic_read(APIC_LVT1);
value &= ~(
- APIC_MODE_MASK | APIC_SEND_PENDING |
+ APIC_DM_MASK | APIC_SEND_PENDING |
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
- value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
- value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+ value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING | APIC_DM_NMI;
apic_write(APIC_LVT1, value);
}
}
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index a99f9cce9d..7f9b87f973 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -139,12 +139,12 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
* BIOS has programmed on AP based on BSP's info we saved (since BIOS
* is required to set the same value for all threads/cores).
*/
- if ( (val & APIC_MODE_MASK) != APIC_DM_FIXED
+ if ( (val & APIC_DM_MASK) != APIC_DM_FIXED
|| (val & APIC_VECTOR_MASK) > 0xf )
apic_write(APIC_LVTTHMR, val);
if ( (msr_content & (1ULL<<3))
- && (val & APIC_MODE_MASK) == APIC_DM_SMI )
+ && (val & APIC_DM_MASK) == APIC_DM_SMI )
{
if ( c == &boot_cpu_data )
printk(KERN_DEBUG "Thermal monitoring handled by SMI\n");
diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 2e08d2363c..b2e9881e06 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -308,12 +308,12 @@ void vpmu_do_interrupt(void)
vlapic_lvtpc = vlapic_get_reg(vlapic, APIC_LVTPC);
- switch ( GET_APIC_DELIVERY_MODE(vlapic_lvtpc) )
+ switch ( vlapic_lvtpc & APIC_DM_MASK )
{
- case APIC_MODE_FIXED:
+ case APIC_DM_FIXED:
vlapic_set_irq(vlapic, vlapic_lvtpc & APIC_VECTOR_MASK, 0);
break;
- case APIC_MODE_NMI:
+ case APIC_DM_NMI:
sampling->arch.nmi_pending = true;
break;
}
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 405bcd9a1c..71a4b954b0 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -39,7 +39,7 @@
(APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
#define LINT_MASK \
- (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
+ (LVT_MASK | APIC_DM_MASK | APIC_INPUT_POLARITY |\
APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
static const unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
@@ -47,9 +47,9 @@ static const unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
/* LVTT */
LVT_MASK | APIC_TIMER_MODE_MASK,
/* LVTTHMR */
- LVT_MASK | APIC_MODE_MASK,
+ LVT_MASK | APIC_DM_MASK,
/* LVTPC */
- LVT_MASK | APIC_MODE_MASK,
+ LVT_MASK | APIC_DM_MASK,
/* LVT0-1 */
LINT_MASK, LINT_MASK,
/* LVTERR */
@@ -260,7 +260,7 @@ static void vlapic_init_sipi_one(struct vcpu *target,
uint32_t icr)
{
vcpu_pause(target);
- switch ( icr & APIC_MODE_MASK )
+ switch ( icr & APIC_DM_MASK )
{
case APIC_DM_INIT: {
bool fpu_initialised;
@@ -329,7 +329,7 @@ static void vlapic_accept_irq(struct vcpu *v, uint32_t
icr_low)
struct vlapic *vlapic = vcpu_vlapic(v);
uint8_t vector = (uint8_t)icr_low;
- switch ( icr_low & APIC_MODE_MASK )
+ switch ( icr_low & APIC_DM_MASK )
{
case APIC_DM_FIXED:
case APIC_DM_LOWEST:
@@ -488,7 +488,7 @@ void vlapic_ipi(
dest = _VLAPIC_ID(vlapic, icr_high);
- switch ( icr_low & APIC_MODE_MASK )
+ switch ( icr_low & APIC_DM_MASK )
{
case APIC_DM_INIT:
case APIC_DM_STARTUP:
@@ -993,7 +993,7 @@ int guest_wrmsr_x2apic(struct vcpu *v, uint32_t msr,
uint64_t val)
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_CMCI:
- if ( val & ~(LVT_MASK | APIC_MODE_MASK) )
+ if ( val & ~(LVT_MASK | APIC_DM_MASK) )
return X86EMUL_EXCEPTION;
break;
@@ -1017,7 +1017,7 @@ int guest_wrmsr_x2apic(struct vcpu *v, uint32_t msr,
uint64_t val)
break;
case APIC_ICR:
- if ( (uint32_t)val & ~(APIC_VECTOR_MASK | APIC_MODE_MASK |
+ if ( (uint32_t)val & ~(APIC_VECTOR_MASK | APIC_DM_MASK |
APIC_DEST_MASK | APIC_INT_ASSERT |
APIC_INT_LEVELTRIG | APIC_SHORT_MASK) )
return X86EMUL_EXCEPTION;
@@ -1266,7 +1266,7 @@ static int __vlapic_accept_pic_intr(struct vcpu *v)
redir0.fields.dest_id == VLAPIC_ID(vlapic) &&
!vlapic_disabled(vlapic)) ||
/* LAPIC has LVT0 unmasked for ExtInts? */
- ((lvt0 & (APIC_MODE_MASK|APIC_LVT_MASKED)) == APIC_DM_EXTINT) ||
+ ((lvt0 & (APIC_DM_MASK | APIC_LVT_MASKED)) == APIC_DM_EXTINT) ||
/* LAPIC is fully disabled? */
vlapic_hw_disabled(vlapic)));
}
diff --git a/xen/arch/x86/include/asm/apicdef.h
b/xen/arch/x86/include/asm/apicdef.h
index c4068ccc10..b0790fad1c 100644
--- a/xen/arch/x86/include/asm/apicdef.h
+++ b/xen/arch/x86/include/asm/apicdef.h
@@ -68,6 +68,7 @@
#define APIC_DEST_MASK 0x00800
#define APIC_DEST_LOGICAL 0x00800
#define APIC_DEST_PHYSICAL 0x00000
+#define APIC_DM_MASK 0x00700
#define APIC_DM_FIXED 0x00000
#define APIC_DM_LOWEST 0x00100
#define APIC_DM_SMI 0x00200
@@ -95,12 +96,6 @@
#define APIC_LVT_REMOTE_IRR (1<<14)
#define APIC_INPUT_POLARITY (1<<13)
#define APIC_SEND_PENDING (1<<12)
-#define APIC_MODE_MASK 0x700
-#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
-#define SET_APIC_DELIVERY_MODE(x,y)
(((x)&~0x700)|((y)<<8))
-#define APIC_MODE_FIXED 0x0
-#define APIC_MODE_NMI 0x4
-#define APIC_MODE_EXTINT 0x7
#define APIC_LVT1 0x360
#define APIC_LVTERR 0x370
#define APIC_TMICT 0x380
diff --git a/xen/arch/x86/oprofile/nmi_int.c b/xen/arch/x86/oprofile/nmi_int.c
index 1313818af8..fa3071d977 100644
--- a/xen/arch/x86/oprofile/nmi_int.c
+++ b/xen/arch/x86/oprofile/nmi_int.c
@@ -290,7 +290,7 @@ static void cf_check nmi_cpu_stop(void *dummy)
* power on apic lvt contain a zero vector nr which are legal only for
* NMI delivery mode. So inhibit apic err before restoring lvtpc
*/
- if ( (apic_read(APIC_LVTPC) & APIC_MODE_MASK) != APIC_DM_NMI
+ if ( (apic_read(APIC_LVTPC) & APIC_DM_MASK) != APIC_DM_NMI
|| (apic_read(APIC_LVTPC) & APIC_LVT_MASKED) )
{
printk("nmi_stop: APIC not good %ul\n", apic_read(APIC_LVTPC));
--
generated by git-patchbot for /home/xen/git/xen.git#master
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