[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86/spec-ctrl: Expose RRSBA_CTRL to guests
commit 478e4787fa64b621061177a7843c452e9a19916d Author: Roger Pau Monné <roger.pau@xxxxxxxxxx> AuthorDate: Tue Jan 30 10:13:59 2024 +0100 Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> CommitDate: Thu Feb 1 19:52:44 2024 +0000 x86/spec-ctrl: Expose RRSBA_CTRL to guests The CPUID feature bit signals the presence of the RRSBA_DIS_{U,S} controls in SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs. Xen already knows how to context switch MSR_SPEC_CTRL properly between guest and hypervisor context. Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- xen/arch/x86/msr.c | 2 ++ xen/include/public/arch-x86/cpufeatureset.h | 2 +- xen/tools/gen-cpuid.py | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 54d3752e93..d42f5bd6ef 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -326,6 +326,8 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp) (psfd ? SPEC_CTRL_PSFD : 0) | (cp->feat.ipred_ctrl ? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) | + (cp->feat.rrsba_ctrl + ? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) | 0); } diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index e586e141c3..bade4edab3 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -303,7 +303,7 @@ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory /* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */ XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */ XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */ -XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /* MSR_SPEC_CTRL.RRSBA_DIS_* */ +XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */ XEN_CPUFEATURE(DDP_CTRL, 13*32+ 3) /* MSR_SPEC_CTRL.DDP_DIS_U */ XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /* MSR_SPEC_CTRL.BHI_DIS_S */ XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 45fab5e75d..1c6d762441 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -320,7 +320,7 @@ def crunch_numbers(state): # as dependent features simplifies Xen's logic, and prevents the guest # from seeing implausible configurations. IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS, - IPRED_CTRL], + IPRED_CTRL, RRSBA_CTRL], IBRS: [AMD_STIBP, AMD_SSBD, PSFD, AUTO_IBRS, IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE], IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE], -- generated by git-patchbot for /home/xen/git/xen.git#master
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