[xen staging-4.18] x86: Resync intel-family.h from Linux

[patchbot@xxxxxxx]

commit b91c253e81db915f685b29e6947144ab9905388d
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Feb 27 16:07:39 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Mar 12 11:36:41 2024 +0000

    x86: Resync intel-family.h from Linux
    
    From v6.8-rc6
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    (cherry picked from commit 195e75371b13c4f7ecdf7b5c50aed0d02f2d7ce8)
---
 xen/arch/x86/include/asm/intel-family.h | 38 +++++++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/intel-family.h 
b/xen/arch/x86/include/asm/intel-family.h
index ffc49151be..b65e9c46b9 100644
--- a/xen/arch/x86/include/asm/intel-family.h
+++ b/xen/arch/x86/include/asm/intel-family.h
@@ -26,6 +26,9 @@
  *             _G      - parts with extra graphics on
  *             _X      - regular server parts
  *             _D      - micro server parts
+ *             _N,_P   - other mobile parts
+ *             _H      - premium mobile parts
+ *             _S      - other client parts
  *
  *             Historical OPTDIFFs:
  *
@@ -37,6 +40,9 @@
  * their own names :-(
  */
 
+/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
+#define INTEL_FAM6_ANY                 X86_MODEL_ANY
+
 #define INTEL_FAM6_CORE_YONAH          0x0E
 
 #define INTEL_FAM6_CORE2_MEROM         0x0F
@@ -93,8 +99,6 @@
 #define INTEL_FAM6_ICELAKE_L           0x7E    /* Sunny Cove */
 #define INTEL_FAM6_ICELAKE_NNPI                0x9D    /* Sunny Cove */
 
-#define INTEL_FAM6_LAKEFIELD           0x8A    /* Sunny Cove / Tremont */
-
 #define INTEL_FAM6_ROCKETLAKE          0xA7    /* Cypress Cove */
 
 #define INTEL_FAM6_TIGERLAKE_L         0x8C    /* Willow Cove */
@@ -102,12 +106,31 @@
 
 #define INTEL_FAM6_SAPPHIRERAPIDS_X    0x8F    /* Golden Cove */
 
+#define INTEL_FAM6_EMERALDRAPIDS_X     0xCF
+
+#define INTEL_FAM6_GRANITERAPIDS_X     0xAD
+#define INTEL_FAM6_GRANITERAPIDS_D     0xAE
+
+/* "Hybrid" Processors (P-Core/E-Core) */
+
+#define INTEL_FAM6_LAKEFIELD           0x8A    /* Sunny Cove / Tremont */
+
 #define INTEL_FAM6_ALDERLAKE           0x97    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L         0x9A    /* Golden Cove / Gracemont */
 
-#define INTEL_FAM6_RAPTORLAKE          0xB7
+#define INTEL_FAM6_RAPTORLAKE          0xB7    /* Raptor Cove / Enhanced 
Gracemont */
+#define INTEL_FAM6_RAPTORLAKE_P                0xBA
+#define INTEL_FAM6_RAPTORLAKE_S                0xBF
+
+#define INTEL_FAM6_METEORLAKE          0xAC
+#define INTEL_FAM6_METEORLAKE_L                0xAA
+
+#define INTEL_FAM6_ARROWLAKE_H         0xC5
+#define INTEL_FAM6_ARROWLAKE           0xC6
+
+#define INTEL_FAM6_LUNARLAKE_M         0xBD
 
-/* "Small Core" Processors (Atom) */
+/* "Small Core" Processors (Atom/E-Core) */
 
 #define INTEL_FAM6_ATOM_BONNELL                0x1C /* Diamondville, Pineview 
*/
 #define INTEL_FAM6_ATOM_BONNELL_MID    0x26 /* Silverthorne, Lincroft */
@@ -134,6 +157,13 @@
 #define INTEL_FAM6_ATOM_TREMONT                0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L      0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_ATOM_GRACEMONT      0xBE /* Alderlake N */
+
+#define INTEL_FAM6_ATOM_CRESTMONT_X    0xAF /* Sierra Forest */
+#define INTEL_FAM6_ATOM_CRESTMONT      0xB6 /* Grand Ridge */
+
+#define INTEL_FAM6_ATOM_DARKMONT_X     0xDD /* Clearwater Forest */
+
 /* Xeon Phi */
 
 #define INTEL_FAM6_XEON_PHI_KNL                0x57 /* Knights Landing */
--
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