[xen staging] arm/gicv3: Fix ICH_VTR_EL2.ListRegs mask

[patchbot@xxxxxxx]

commit 3502c033f6d60e5fc944e66d7bd1c3c6456caae7
Author:     Michal Orzel <michal.orzel@xxxxxxx>
AuthorDate: Tue Sep 3 14:21:47 2024 +0200
Commit:     Julien Grall <jgrall@xxxxxxxxxx>
CommitDate: Wed Sep 11 10:59:42 2024 +0100

    arm/gicv3: Fix ICH_VTR_EL2.ListRegs mask
    
    According to GIC spec IHI 0069H.b (12.4.9), the ListRegs field of
    ICH_VTR_EL2 can have value between 0b00000..0b01111, as there can
    be maximum 16 LRs (field value + 1). Fix the mask used to extract this
    value which wrongly assumes there can be 64 (case for GICv2).
    
    Fixes: bc183a0235e0 ("xen/arm: Add support for GIC v3")
    Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h 
b/xen/arch/arm/include/asm/gic_v3_defs.h
index 227533868f..2af093e774 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -189,7 +189,7 @@
 #define ICH_LR_GRP1                  (1ULL << 60)
 #define ICH_LR_HW                    (1ULL << 61)
 
-#define ICH_VTR_NRLRGS               0x3f
+#define ICH_VTR_NRLRGS               0xf
 #define ICH_VTR_PRIBITS_MASK         0x7
 #define ICH_VTR_PRIBITS_SHIFT        29
 
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