[xen staging] x86/time: address violations of MISRA C Rule 16.3

[patchbot@xxxxxxx]

commit b3173a25ba8b766e4cba701d79333935d8ccf3c2
Author:     Federico Serafini <federico.serafini@xxxxxxxxxxx>
AuthorDate: Wed Sep 11 12:54:52 2024 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Sep 11 12:54:52 2024 +0200

    x86/time: address violations of MISRA C Rule 16.3
    
    Address violations of MISRA C:2012 Rule 16.3:
    "An unconditional `break' statement shall terminate every
    switch-clause".
    
    No functional change.
    
    Signed-off-by: Federico Serafini <federico.serafini@xxxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/time.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 1dcbd9f520..9588502f28 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1467,6 +1467,7 @@ unsigned int rtc_guest_read(unsigned int port)
 
     default:
         ASSERT_UNREACHABLE();
+        break;
     }
 
     return data;
@@ -1519,6 +1520,7 @@ void rtc_guest_write(unsigned int port, unsigned int data)
 
     default:
         ASSERT_UNREACHABLE();
+        break;
     }
 }
 
--
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