[qemu-xen staging-4.19] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

[patchbot@xxxxxxx]

commit ee638bc5b53cff87768b0b7c6d2c4a4e275994f6
Author:     Nathan Egge <negge@xxxxxxxx>
AuthorDate: Thu Aug 3 09:14:24 2023 -0400
Commit:     Michael Tokarev <mjt@xxxxxxxxxx>
CommitDate: Sun Sep 10 19:39:41 2023 +0300

    linux-user/elfload: Set V in ELF_HWCAP for RISC-V
    
    Set V bit for hwcap if misa is set.
    
    Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
    Signed-off-by: Nathan Egge <negge@xxxxxxxx>
    Reviewed-by: Daniel Henrique Barboza <dbarboza@xxxxxxxxxxxxxxxx>
    Tested-by: Daniel Henrique Barboza <dbarboza@xxxxxxxxxxxxxxxx>
    Message-Id: <20230803131424.40744-1-negge@xxxxxxxx>
    Signed-off-by: Richard Henderson <richard.henderson@xxxxxxxxxx>
    (cherry picked from commit 4333f0924c2f2ca8efaebaed8c24f55f77d8b013)
    Signed-off-by: Michael Tokarev <mjt@xxxxxxxxxx>
---
 linux-user/elfload.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 88ef26dc03..a3e78a7e18 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1679,7 +1679,8 @@ static uint32_t get_elf_hwcap(void)
 #define MISA_BIT(EXT) (1 << (EXT - 'A'))
     RISCVCPU *cpu = RISCV_CPU(thread_cpu);
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V');
 
     return cpu->env.misa_ext & mask;
 #undef MISA_BIT
--
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