[qemu-xen staging-4.18] target/arm: Fix 64-bit SSRA

[patchbot@xxxxxxx]

commit d4c0ac705d720e19d9ec5b9fe1c6c7bb22b6913a
Author:     Richard Henderson <richard.henderson@xxxxxxxxxx>
AuthorDate: Tue Aug 22 17:31:14 2023 +0100
Commit:     Michael Tokarev <mjt@xxxxxxxxxx>
CommitDate: Sun Sep 10 19:39:41 2023 +0300

    target/arm: Fix 64-bit SSRA
    
    Typo applied byte-wise shift instead of double-word shift.
    
    Cc: qemu-stable@xxxxxxxxxx
    Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
    Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
    Signed-off-by: Richard Henderson <richard.henderson@xxxxxxxxxx>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@xxxxxxxxxx>
    Message-id: 20230821022025.397682-1-richard.henderson@xxxxxxxxxx
    Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
    (cherry picked from commit cd1e4db73646006039f25879af3bff55b2295ff3)
    Signed-off-by: Michael Tokarev <mjt@xxxxxxxxxx>
---
 target/arm/tcg/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 1e4d94e58a..e1fe68f73a 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -3063,7 +3063,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, 
uint32_t rm_ofs,
           .vece = MO_32 },
         { .fni8 = gen_ssra64_i64,
           .fniv = gen_ssra_vec,
-          .fno = gen_helper_gvec_ssra_b,
+          .fno = gen_helper_gvec_ssra_d,
           .prefer_i64 = TCG_TARGET_REG_BITS == 64,
           .opt_opc = vecop_list,
           .load_dest = true,
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging-4.18