[qemu-xen staging-4.18] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes

[patchbot@xxxxxxx]

commit 70c97e75d709eadf80845259ea0a0409475102c3
Author:     Leon Schuermann <leons@xxxxxxxxxxxxx>
AuthorDate: Tue Aug 29 17:50:46 2023 -0400
Commit:     Michael Tokarev <mjt@xxxxxxxxxx>
CommitDate: Wed Sep 20 10:18:14 2023 +0300

    target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
    
    When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
    configuration lock bits must not apply. While this behavior is
    implemented for the pmpcfgX CSRs, this bit is not respected for
    changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
    writes work even on locked regions when the global rule-lock bypass is
    enabled.
    
    Signed-off-by: Leon Schuermann <leons@xxxxxxxxxxxxx>
    Reviewed-by: Mayuresh Chitale <mchitale@xxxxxxxxxxxxxxxx>
    Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
    Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
    (cherry picked from commit 4e3adce1244e1ca30ec05874c3eca14911dc0825)
    Signed-off-by: Michael Tokarev <mjt@xxxxxxxxxx>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index a08cd95658..bcb4baa0a2 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -45,6 +45,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
  */
 static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
 {
+    /* mseccfg.RLB is set */
+    if (MSECCFG_RLB_ISSET(env)) {
+        return 0;
+    }
 
     if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
         return 1;
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging-4.18