[xen staging] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing

[patchbot@xxxxxxx]

commit 35b61d5f465d085a69772e5c769fc1a38984dd97
Author:     Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>
AuthorDate: Tue Sep 9 10:09:23 2025 +0000
Commit:     Stefano Stabellini <stefano.stabellini@xxxxxxx>
CommitDate: Tue Sep 9 16:32:01 2025 -0700

    xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
    
    To properly deactivate physical eSPI routed to a domain and allow them to
    be retriggered after the initial trigger, the LR needs to be updated. The
    current implementation ignores interrupts outside the range specified by
    the mask 0x3FF, which only covers IRQ numbers up to 1023. To enable
    processing of eSPI interrupts, this patch updates the mask to 0x1FFF.
    
    Signed-off-by: Leonid Komarianskyi <leonid_komarianskyi@xxxxxxxx>
    Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Acked-by: Julien Grall <jgrall@xxxxxxxxxx>
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h 
b/xen/arch/arm/include/asm/gic_v3_defs.h
index 3370b4cd52..c373b94d19 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -211,7 +211,7 @@
 #define ICH_LR_VIRTUAL_SHIFT         0
 #define ICH_LR_CPUID_MASK            0x7
 #define ICH_LR_CPUID_SHIFT           10
-#define ICH_LR_PHYSICAL_MASK         0x3ff
+#define ICH_LR_PHYSICAL_MASK         0x1fff
 #define ICH_LR_PHYSICAL_SHIFT        32
 #define ICH_LR_STATE_MASK            0x3
 #define ICH_LR_STATE_SHIFT           62
--
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