[xen staging] xen/arm: domain_build/dom0less-build: adjust domains config to support eSPIs

[patchbot@xxxxxxx]

commit b5861cf1114692906db62c36dde5684a2d1ac3be
Author:     Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>
AuthorDate: Tue Sep 9 10:09:29 2025 +0000
Commit:     Stefano Stabellini <stefano.stabellini@xxxxxxx>
CommitDate: Tue Sep 9 16:32:04 2025 -0700

    xen/arm: domain_build/dom0less-build: adjust domains config to support eSPIs
    
    The Dom0 and DomUs logic for the dom0less configuration in create_dom0()
    and arch_create_domUs() should account for extended SPIs when supported
    by the hardware and enabled with CONFIG_GICV3_ESPI. These changes ensure
    proper calculation of the maximum number of SPIs and eSPIs available to
    Dom0 and DomUs in dom0less setups.
    
    When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled, 
the
    maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID
    offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure
    compatibility with non-Dom0 domains, this adjustment is applied by the
    toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is
    handled directly during VGIC initialization. If eSPIs are not supported, the
    calculation defaults to using the standard SPI range, with a maximum value 
of
    992 interrupt lines, as it works currently.
    
    Signed-off-by: Leonid Komarianskyi <leonid_komarianskyi@xxxxxxxx>
    Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Reviewed-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@xxxxxxxx>
    Acked-by: Julien Grall <jgrall@xxxxxxxxxx>
---
 xen/arch/arm/dom0less-build.c   |  2 +-
 xen/arch/arm/domain_build.c     |  2 +-
 xen/arch/arm/include/asm/vgic.h | 19 +++++++++++++++++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index f00912a1ca..4181c10538 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -326,7 +326,7 @@ int __init arch_parse_dom0less_node(struct dt_device_node 
*node,
     {
         int vpl011_virq = GUEST_VPL011_SPI;
 
-        d_cfg->arch.nr_spis = VGIC_DEF_NR_SPIS;
+        d_cfg->arch.nr_spis = vgic_def_nr_spis();
 
         /*
          * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 89448fb475..fb8fbb1650 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2063,7 +2063,7 @@ void __init create_dom0(void)
 
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
     dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
-    dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
+    dom0_cfg.arch.nr_spis = vgic_def_nr_spis();
     dom0_cfg.arch.tee_type = tee_get_type();
     dom0_cfg.max_vcpus = dom0_max_vcpus();
 
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
index caffea092b..24a4a968c3 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -357,6 +357,25 @@ extern void vgic_check_inflight_irqs_pending(struct vcpu 
*v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
 
+static inline unsigned int vgic_def_nr_spis(void)
+{
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the appropriate
+     * config is set). If not, the common SPI range will be used. Otherwise
+     * return the maximum eSPI INTID, supported by HW GIC, subtracted by 32.
+     * For Dom0 and started at boot time DomUs we will add back this value
+     * during VGIC initialization. This ensures consistent handling for Dom0
+     * and other domains. For the regular SPI range interrupts in this case,
+     * the maximum value of VGIC_DEF_NR_SPIS will be used.
+     */
+    if ( gic_number_espis() > 0 )
+        return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
+#endif
+
+    return VGIC_DEF_NR_SPIS;
+}
+
 extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
 
 static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
--
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