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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging-4.21] x86/fsgsbase: Update fs/gs helpers to use wrmsrns()
commit 447a046a439aea36a66ce1ea21bad96c21940ac1
Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Thu Aug 14 15:26:56 2025 +0100
Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Mar 17 12:13:49 2026 +0000
x86/fsgsbase: Update fs/gs helpers to use wrmsrns()
... and rdmsr() while here.
Most of these accesses are in fastpaths and do not need serialising
behaviour,
but the write side is serialising on all Intel hardware as well as older AMD
hardware.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
(cherry picked from commit 6b448a92a367839386994def3209c079fc98fe68)
---
xen/arch/x86/domain.c | 10 +++++-----
xen/arch/x86/hvm/vmx/vmx.c | 4 ++--
xen/arch/x86/include/asm/fsgsbase.h | 30 +++++++++---------------------
3 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index d488f08aff..7d74414ada 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1847,9 +1847,9 @@ static void load_segments(struct vcpu *n)
}
else
{
- wrmsrl(MSR_FS_BASE, n->arch.pv.fs_base);
- wrmsrl(MSR_GS_BASE, gsb);
- wrmsrl(MSR_SHADOW_GS_BASE, gss);
+ wrmsrns(MSR_FS_BASE, n->arch.pv.fs_base);
+ wrmsrns(MSR_GS_BASE, gsb);
+ wrmsrns(MSR_SHADOW_GS_BASE, gss);
}
}
@@ -1974,8 +1974,8 @@ static void save_segments(struct vcpu *v)
}
else
{
- rdmsrl(MSR_FS_BASE, fs_base);
- rdmsrl(MSR_GS_BASE, gs_base);
+ fs_base = rdmsr(MSR_FS_BASE);
+ gs_base = rdmsr(MSR_GS_BASE);
}
v->arch.pv.fs_base = fs_base;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index a4f606720f..1d464324ec 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2737,8 +2737,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v,
unsigned int reg)
case MSR_SHADOW_GS_BASE:
if ( v != curr )
return v->arch.hvm.vmx.shadow_gs;
- rdmsrl(MSR_SHADOW_GS_BASE, val);
- return val;
+ else
+ return rdmsr(MSR_SHADOW_GS_BASE);
}
/* Logic which maybe requires remote VMCS acquisition. */
diff --git a/xen/arch/x86/include/asm/fsgsbase.h
b/xen/arch/x86/include/asm/fsgsbase.h
index 5577038426..24862a6bfe 100644
--- a/xen/arch/x86/include/asm/fsgsbase.h
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -63,38 +63,26 @@ static inline void __wrgs_shadow(unsigned long base)
static inline unsigned long read_fs_base(void)
{
- unsigned long base;
-
if ( read_cr4() & X86_CR4_FSGSBASE )
return __rdfsbase();
-
- rdmsrl(MSR_FS_BASE, base);
-
- return base;
+ else
+ return rdmsr(MSR_FS_BASE);
}
static inline unsigned long read_gs_base(void)
{
- unsigned long base;
-
if ( read_cr4() & X86_CR4_FSGSBASE )
return __rdgsbase();
-
- rdmsrl(MSR_GS_BASE, base);
-
- return base;
+ else
+ return rdmsr(MSR_GS_BASE);
}
static inline unsigned long read_gs_shadow(void)
{
- unsigned long base;
-
if ( read_cr4() & X86_CR4_FSGSBASE )
return __rdgs_shadow();
-
- rdmsrl(MSR_SHADOW_GS_BASE, base);
-
- return base;
+ else
+ return rdmsr(MSR_SHADOW_GS_BASE);
}
static inline void write_fs_base(unsigned long base)
@@ -102,7 +90,7 @@ static inline void write_fs_base(unsigned long base)
if ( read_cr4() & X86_CR4_FSGSBASE )
__wrfsbase(base);
else
- wrmsrl(MSR_FS_BASE, base);
+ wrmsrns(MSR_FS_BASE, base);
}
static inline void write_gs_base(unsigned long base)
@@ -110,7 +98,7 @@ static inline void write_gs_base(unsigned long base)
if ( read_cr4() & X86_CR4_FSGSBASE )
__wrgsbase(base);
else
- wrmsrl(MSR_GS_BASE, base);
+ wrmsrns(MSR_GS_BASE, base);
}
static inline void write_gs_shadow(unsigned long base)
@@ -118,7 +106,7 @@ static inline void write_gs_shadow(unsigned long base)
if ( read_cr4() & X86_CR4_FSGSBASE )
__wrgs_shadow(base);
else
- wrmsrl(MSR_SHADOW_GS_BASE, base);
+ wrmsrns(MSR_SHADOW_GS_BASE, base);
}
#endif /* X86_FSGSBASE_H */
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.21
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