[xen staging] x86/vpmu: Expose up to 8 Intel event selectors in PV Dom0

[patchbot@xxxxxxx]

commit 4e9d9e7cc9a663d7c15118d5ebe344f7edad3ec9
Author:     Teddy Astie <teddy.astie@xxxxxxxxxx>
AuthorDate: Tue Mar 24 12:04:46 2026 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Mar 24 12:04:46 2026 +0100

    x86/vpmu: Expose up to 8 Intel event selectors in PV Dom0
    
    Most (if not all) Intel CPUs starting from Sandy Bridge have up to 8
    event selectors per core, which could be halved per hyperthread.
    
    However, current PV emulation logic doesn't support up to 8 event selector,
    leading to errors when trying to access them, hence, preventing Linux from
    driving the vPMU correctly.
    
    Make sure up to MSR_P6_EVNTSEL(7) is usable, which is the same upper bound 
as
    used in VMX code.
    
    The check if the event selector actually exist for the hardware is done in
    core2_vpmu_do_{rdmsr,wrmsr}, hence we're not allowing to access non-existent
    MSRs.
    
    Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV 
guests")
    Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/pv/emul-priv-op.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 53676b3021..d98c7f166a 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -992,7 +992,7 @@ static int cf_check read_msr(
         return X86EMUL_OKAY;
 
     case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7):
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
         if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
@@ -1175,7 +1175,7 @@ static int cf_check write_msr(
         break;
 
     case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7):
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
         if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
--
generated by git-patchbot for /home/xen/git/xen.git#staging