[xen master] x86/vlapic: Don't change ICR on x2APIC SELF_IPI write

[patchbot@xxxxxxx]

commit 6a5329819bb6951b0d191a9d2d617a78b3bbd9fa
Author:     Teddy Astie <teddy.astie@xxxxxxxxxx>
AuthorDate: Thu Oct 29 09:12:24 2026 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Oct 29 09:12:24 2026 +0100

    x86/vlapic: Don't change ICR on x2APIC SELF_IPI write
    
    The Intel SDM (Vol 3A-13.12.11, June 2026) says
    
    > The semantics of sending a self-IPI via the SELF IPI register
    > are identical to sending a self targeted edge triggered fixed
    > interrupt with the specified vector.
    
    However, this doesn't require altering the ICR register.
    On most Intel processors (at least Core/P-Core), it does alter ICR,
    but it's not the case on AMD and Atom/E-Core ones, and APICv Self-IPI
    appears to follow a similar behavior.
    
    For consistency, adjust the Xen behavior to send the Self-IPI
    directly instead of emulating it by modifying ICR register.
    
    It also clarify the logic.
    
    Assisted-by: Claude Fable 5.1
    Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/hvm/vlapic.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 885f5d304b..0d7231c45b 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -973,8 +973,8 @@ int vlapic_apicv_write(struct vcpu *v, unsigned int offset)
         if ( offset != APIC_SELF_IPI )
             return X86EMUL_UNHANDLEABLE;
 
-        offset = APIC_ICR;
-        val = APIC_DEST_SELF | (val & APIC_VECTOR_MASK);
+        vlapic_ipi(vlapic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
+        return X86EMUL_OKAY;
     }
 
     vlapic_reg_write(v, offset, val);
@@ -1050,9 +1050,8 @@ int guest_wrmsr_x2apic(struct vcpu *v, uint32_t msr, 
uint64_t val)
     case APIC_SELF_IPI:
         if ( val & ~APIC_VECTOR_MASK )
             return X86EMUL_EXCEPTION;
-        offset = APIC_ICR;
-        val = APIC_DEST_SELF | (val & APIC_VECTOR_MASK);
-        break;
+        vlapic_ipi(vlapic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
+        return X86EMUL_OKAY;
 
     case APIC_EOI:
     case APIC_ESR:
--
generated by git-patchbot for /home/xen/git/xen.git#master