[xen staging-4.21] x86/ACPI: optimise C3 entry on AMD CPUs

[patchbot@xxxxxxx]

commit ddb3e7acdf3d846d9dd029b10ee3251b245d6ddf
Author:     Deepak Sharma <deepak.sharma@xxxxxxx>
AuthorDate: Thu Oct 29 13:22:41 2026 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Oct 29 13:22:41 2026 +0100

    x86/ACPI: optimise C3 entry on AMD CPUs
    
    All Zen or newer CPU which support C3 shares cache. Its not necessary to
    flush the caches in software before entering C3. This will cause drop in
    performance for the cores which share some caches. ARB_DIS is not used
    with current AMD C state implementation. So set related flags correctly.
    
    Signed-off-by: Deepak Sharma <deepak.sharma@xxxxxxx>
    Acked-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
    Origin: https://git.kernel.org/torvalds/p/a8fb40966f19
    [Port to Xen.  Include Hygon.]
    Assisted-by: Claude-Code:claude-opus-5-5
    Signed-off-by: Olivier Lambert <olivier.lambert@xxxxxxxxxx>
    Reviewed-by: Jason Andryuk <jason.andryuk@xxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: f9b72572c8d5b6d312fd0b5014f65bed20efac40
    master date: 2026-10-01 10:00:35 +0200
---
 xen/arch/x86/acpi/cpu_idle.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 3e4d9730aa..1cdcd12f66 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1066,6 +1066,24 @@ static void acpi_processor_power_init_bm_check(struct 
acpi_processor_flags *flag
     if ( c->x86_vendor == X86_VENDOR_INTEL &&
         (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)) )
             flags->bm_control = 0;
+
+    if ( (c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) &&
+         c->x86 >= 0x17 )
+    {
+        /*
+         * For all AMD Zen or newer CPUs that support C3, caches
+         * should not be flushed by software while entering C3
+         * type state. Set bm_check to 1 so that Xen doesn't
+         * need to execute cache flush operation.
+         */
+        flags->bm_check = 1;
+        /*
+         * In current AMD C state implementation ARB_DIS is no longer
+         * used. So set bm_control to zero to indicate ARB_DIS is not
+         * required while entering C3 type state.
+         */
+        flags->bm_control = 0;
+    }
 }
 
 #define VENDOR_INTEL                   (1)
--
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