diff -r 0268e7380953 xen/arch/x86/io_apic.c --- a/xen/arch/x86/io_apic.c Mon Sep 05 15:10:28 2011 +0100 +++ b/xen/arch/x86/io_apic.c Thu Sep 08 14:17:31 2011 +0100 @@ -357,7 +357,7 @@ static void __eoi_IO_APIC_irq(unsigned i pin = entry->pin; if (pin == -1) break; - io_apic_eoi(entry->apic, vector); + io_apic_eoi_vector(entry->apic, vector); if (!entry->next) break; entry = irq_2_pin + entry->next; @@ -397,18 +397,7 @@ static void clear_IO_APIC_pin(unsigned i entry.trigger = 1; __ioapic_write_entry(apic, pin, TRUE, entry); } - if (mp_ioapics[apic].mpc_apicver >= 0x20) - io_apic_eoi(apic, entry.vector); - else { - /* - * Mechanism by which we clear remoteIRR in this case is by - * changing the trigger mode to edge and back to level. - */ - entry.trigger = 0; - __ioapic_write_entry(apic, pin, TRUE, entry); - entry.trigger = 1; - __ioapic_write_entry(apic, pin, TRUE, entry); - } + io_apic_eoi_pin(apic, pin); } /* @@ -1750,7 +1739,7 @@ static void end_level_ioapic_irq (unsign { int ioapic; for (ioapic = 0; ioapic < nr_ioapics; ioapic++) - io_apic_eoi(ioapic, i); + io_apic_eoi_vector(ioapic, i); } v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); @@ -2622,3 +2611,67 @@ void __init init_ioapic_mappings(void) printk(XENLOG_INFO "IRQ limits: %u GSI, %u MSI/MSI-X\n", nr_irqs_gsi, nr_irqs - nr_irqs_gsi); } + +/* EOI an IO-APIC entry given the vector it points to */ +void io_apic_eoi_vector(unsigned int apic, unsigned int vector) +{ + unsigned int flags; + + spin_lock_irqsave(&ioapic_lock, flags); + + if ( ioapic_has_eoi_reg(apic) ) + /* Prefer the use of the EOI register if available */ + *(IO_APIC_BASE(apic)+16) = vector; + else + { + /* Else search through the IO-APIC entries to find the + * correct pin */ + struct IO_APIC_route_entry entry; + unsigned int pin = 0; + + do + { + entry = __ioapic_read_entry(apic, pin, TRUE); + + if ( entry.vector == vector ) + { + /* And if found, fake an EOI by flipping the + * trigger mode to edge and back */ + entry.trigger = 0; + __ioapic_write_entry(apic, pin, TRUE, entry); + entry.trigger = 1; + __ioapic_write_entry(apic, pin, TRUE, entry); + break; + } + + } while ( pin++ < nr_ioapic_registers[apic] ); + } + + spin_unlock_irqrestore(&ioapic_lock, flags); +} + +/* EOI an IO-APIC entry given its pin */ +void io_apic_eoi_pin(unsigned int apic, unsigned int pin) +{ + struct IO_APIC_route_entry entry; + unsigned int flags; + + entry = __ioapic_read_entry(apic, pin, TRUE); + + spin_lock_irqsave(&ioapic_lock, flags); + + if ( ioapic_has_eoi_reg(apic) ) + /* Prefer the use of the EOI register if available */ + *(IO_APIC_BASE(apic)+16) = entry.vector; + else + { + /* Else fake an EOI by switching to edge triggered mode + * and back */ + entry.trigger = 0; + __ioapic_write_entry(apic, pin, TRUE, entry); + entry.trigger = 1; + __ioapic_write_entry(apic, pin, TRUE, entry); + } + + spin_unlock_irqrestore(&ioapic_lock, flags); +} diff -r 0268e7380953 xen/include/asm-x86/io_apic.h --- a/xen/include/asm-x86/io_apic.h Mon Sep 05 15:10:28 2011 +0100 +++ b/xen/include/asm-x86/io_apic.h Thu Sep 08 14:17:31 2011 +0100 @@ -157,10 +157,9 @@ static inline void io_apic_write(unsigne __io_apic_write(apic, reg, value); } -static inline void io_apic_eoi(unsigned int apic, unsigned int vector) -{ - *(IO_APIC_BASE(apic)+16) = vector; -} +#define ioapic_has_eoi_reg(apic) (mp_ioapics[(apic)].mpc_apicver >= 0x20) +void io_apic_eoi_vector(unsigned int apic, unsigned int vector); +void io_apic_eoi_pin(unsigned int apic, unsigned int pin); /* * Re-write a value: to be used for read-modify-write