Signed-off-by: Jan Beulich --- 2011-09-20.orig/xen/arch/x86/cpu/amd.c 2011-08-16 08:15:46.000000000 +0200 +++ 2011-09-20/xen/arch/x86/cpu/amd.c 2011-08-25 15:13:05.000000000 +0200 @@ -262,15 +262,15 @@ static void disable_c1_ramping(void) int node, nr_nodes; /* Read the number of nodes from the first Northbridge. */ - nr_nodes = ((pci_conf_read32(0, 0x18, 0x0, 0x60)>>4)&0x07)+1; + nr_nodes = ((pci_conf_read32(0, 0, 0x18, 0x0, 0x60)>>4)&0x07)+1; for (node = 0; node < nr_nodes; node++) { /* PMM7: bus=0, dev=0x18+node, function=0x3, register=0x87. */ - pmm7 = pci_conf_read8(0, 0x18+node, 0x3, 0x87); + pmm7 = pci_conf_read8(0, 0, 0x18+node, 0x3, 0x87); /* Invalid read means we've updated every Northbridge. */ if (pmm7 == 0xFF) break; pmm7 &= 0xFC; /* clear pmm7[1:0] */ - pci_conf_write8(0, 0x18+node, 0x3, 0x87, pmm7); + pci_conf_write8(0, 0, 0x18+node, 0x3, 0x87, pmm7); printk ("AMD: Disabling C1 Clock Ramping Node #%x\n", node); } } --- 2011-09-20.orig/xen/arch/x86/dmi_scan.c 2011-09-05 09:12:30.000000000 +0200 +++ 2011-09-20/xen/arch/x86/dmi_scan.c 2011-08-25 15:36:55.000000000 +0200 @@ -284,15 +284,15 @@ static int __init ich10_bios_quirk(struc { u32 port, smictl; - if ( pci_conf_read16(0, 0x1f, 0, PCI_VENDOR_ID) != 0x8086 ) + if ( pci_conf_read16(0, 0, 0x1f, 0, PCI_VENDOR_ID) != 0x8086 ) return 0; - switch ( pci_conf_read16(0, 0x1f, 0, PCI_DEVICE_ID) ) { + switch ( pci_conf_read16(0, 0, 0x1f, 0, PCI_DEVICE_ID) ) { case 0x3a14: case 0x3a16: case 0x3a18: case 0x3a1a: - port = (pci_conf_read16(0, 0x1f, 0, 0x40) & 0xff80) + 0x30; + port = (pci_conf_read16(0, 0, 0x1f, 0, 0x40) & 0xff80) + 0x30; smictl = inl(port); /* turn off LEGACY_USB{,2}_EN if enabled */ if ( smictl & 0x20008 ) --- 2011-09-20.orig/xen/arch/x86/msi.c 2011-08-25 15:06:35.000000000 +0200 +++ 2011-09-20/xen/arch/x86/msi.c 2011-08-25 15:13:05.000000000 +0200 @@ -166,23 +166,25 @@ static void read_msi_msg(struct msi_desc { struct pci_dev *dev = entry->dev; int pos = entry->msi_attrib.pos; - u16 data; + u16 data, seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); - msg->address_lo = pci_conf_read32(bus, slot, func, + msg->address_lo = pci_conf_read32(seg, bus, slot, func, msi_lower_address_reg(pos)); if ( entry->msi_attrib.is_64 ) { - msg->address_hi = pci_conf_read32(bus, slot, func, + msg->address_hi = pci_conf_read32(seg, bus, slot, func, msi_upper_address_reg(pos)); - data = pci_conf_read16(bus, slot, func, msi_data_reg(pos, 1)); + data = pci_conf_read16(seg, bus, slot, func, + msi_data_reg(pos, 1)); } else { msg->address_hi = 0; - data = pci_conf_read16(bus, slot, func, msi_data_reg(pos, 0)); + data = pci_conf_read16(seg, bus, slot, func, + msi_data_reg(pos, 0)); } msg->data = data; break; @@ -231,21 +233,22 @@ static void write_msi_msg(struct msi_des { struct pci_dev *dev = entry->dev; int pos = entry->msi_attrib.pos; + u16 seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); - pci_conf_write32(bus, slot, func, msi_lower_address_reg(pos), + pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), msg->address_lo); if ( entry->msi_attrib.is_64 ) { - pci_conf_write32(bus, slot, func, msi_upper_address_reg(pos), + pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(pos), msg->address_hi); - pci_conf_write16(bus, slot, func, msi_data_reg(pos, 1), + pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 1), msg->data); } else - pci_conf_write16(bus, slot, func, msi_data_reg(pos, 0), + pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 0), msg->data); break; } @@ -295,38 +298,38 @@ void set_msi_affinity(unsigned int irq, static void msi_set_enable(struct pci_dev *dev, int enable) { int pos; - u16 control; + u16 control, seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSI); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); if ( pos ) { - control = pci_conf_read16(bus, slot, func, pos + PCI_MSI_FLAGS); + control = pci_conf_read16(seg, bus, slot, func, pos + PCI_MSI_FLAGS); control &= ~PCI_MSI_FLAGS_ENABLE; if ( enable ) control |= PCI_MSI_FLAGS_ENABLE; - pci_conf_write16(bus, slot, func, pos + PCI_MSI_FLAGS, control); + pci_conf_write16(seg, bus, slot, func, pos + PCI_MSI_FLAGS, control); } } static void msix_set_enable(struct pci_dev *dev, int enable) { int pos; - u16 control; + u16 control, seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSIX); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); if ( pos ) { - control = pci_conf_read16(bus, slot, func, pos + PCI_MSIX_FLAGS); + control = pci_conf_read16(seg, bus, slot, func, pos + PCI_MSIX_FLAGS); control &= ~PCI_MSIX_FLAGS_ENABLE; if ( enable ) control |= PCI_MSIX_FLAGS_ENABLE; - pci_conf_write16(bus, slot, func, pos + PCI_MSIX_FLAGS, control); + pci_conf_write16(seg, bus, slot, func, pos + PCI_MSIX_FLAGS, control); } } @@ -348,15 +351,16 @@ static void msi_set_mask_bit(unsigned in if (entry->msi_attrib.maskbit) { int pos; u32 mask_bits; + u16 seg = entry->dev->seg; u8 bus = entry->dev->bus; u8 slot = PCI_SLOT(entry->dev->devfn); u8 func = PCI_FUNC(entry->dev->devfn); pos = (long)entry->mask_base; - mask_bits = pci_conf_read32(bus, slot, func, pos); + mask_bits = pci_conf_read32(seg, bus, slot, func, pos); mask_bits &= ~(1); mask_bits |= flag; - pci_conf_write32(bus, slot, func, pos, mask_bits); + pci_conf_write32(seg, bus, slot, func, pos, mask_bits); } break; case PCI_CAP_ID_MSIX: @@ -379,7 +383,8 @@ static int msi_get_mask_bit(const struct case PCI_CAP_ID_MSI: if (!entry->dev || !entry->msi_attrib.maskbit) break; - return pci_conf_read32(entry->dev->bus, PCI_SLOT(entry->dev->devfn), + return pci_conf_read32(entry->dev->seg, entry->dev->bus, + PCI_SLOT(entry->dev->devfn), PCI_FUNC(entry->dev->devfn), (unsigned long)entry->mask_base) & 1; case PCI_CAP_ID_MSIX: @@ -473,14 +478,14 @@ static int msi_capability_init(struct pc { struct msi_desc *entry; int pos; - u16 control; + u16 control, seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); ASSERT(spin_is_locked(&pcidevs_lock)); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSI); - control = pci_conf_read16(bus, slot, func, msi_control_reg(pos)); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + control = pci_conf_read16(seg, bus, slot, func, msi_control_reg(pos)); /* MSI Entry Initialization */ msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ @@ -503,12 +508,12 @@ static int msi_capability_init(struct pc { unsigned int maskbits, temp; /* All MSIs are unmasked by default, Mask them all */ - maskbits = pci_conf_read32(bus, slot, func, + maskbits = pci_conf_read32(seg, bus, slot, func, msi_mask_bits_reg(pos, is_64bit_address(control))); temp = (1 << multi_msi_capable(control)); temp = ((temp - 1) & ~temp); maskbits |= temp; - pci_conf_write32(bus, slot, func, + pci_conf_write32(seg, bus, slot, func, msi_mask_bits_reg(pos, is_64bit_address(control)), maskbits); } @@ -516,27 +521,28 @@ static int msi_capability_init(struct pc *desc = entry; /* Restore the original MSI enabled bits */ - pci_conf_write16(bus, slot, func, msi_control_reg(pos), control); + pci_conf_write16(seg, bus, slot, func, msi_control_reg(pos), control); return 0; } -static u64 read_pci_mem_bar(u8 bus, u8 slot, u8 func, u8 bir, int vf) +static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u8 func, u8 bir, int vf) { u8 limit; u32 addr, base = PCI_BASE_ADDRESS_0, disp = 0; if ( vf >= 0 ) { - struct pci_dev *pdev = pci_get_pdev(0, bus, PCI_DEVFN(slot, func)); - unsigned int pos = pci_find_ext_capability(0, bus, + struct pci_dev *pdev = pci_get_pdev(seg, bus, PCI_DEVFN(slot, func)); + unsigned int pos = pci_find_ext_capability(seg, bus, PCI_DEVFN(slot, func), PCI_EXT_CAP_ID_SRIOV); - u16 ctrl = pci_conf_read16(bus, slot, func, pos + PCI_SRIOV_CTRL); - u16 num_vf = pci_conf_read16(bus, slot, func, pos + PCI_SRIOV_NUM_VF); - u16 offset = pci_conf_read16(bus, slot, func, + u16 ctrl = pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV_CTRL); + u16 num_vf = pci_conf_read16(seg, bus, slot, func, + pos + PCI_SRIOV_NUM_VF); + u16 offset = pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV_VF_OFFSET); - u16 stride = pci_conf_read16(bus, slot, func, + u16 stride = pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV_VF_STRIDE); if ( !pdev || !pos || @@ -562,7 +568,8 @@ static u64 read_pci_mem_bar(u8 bus, u8 s disp = vf * pdev->vf_rlen[bir]; limit = PCI_SRIOV_NUM_BARS; } - else switch ( pci_conf_read8(bus, slot, func, PCI_HEADER_TYPE) & 0x7f ) + else switch ( pci_conf_read8(seg, bus, slot, func, + PCI_HEADER_TYPE) & 0x7f ) { case PCI_HEADER_TYPE_NORMAL: limit = 6; @@ -579,7 +586,7 @@ static u64 read_pci_mem_bar(u8 bus, u8 s if ( bir >= limit ) return 0; - addr = pci_conf_read32(bus, slot, func, base + bir * 4); + addr = pci_conf_read32(seg, bus, slot, func, base + bir * 4); if ( (addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO ) return 0; if ( (addr & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64 ) @@ -588,7 +595,8 @@ static u64 read_pci_mem_bar(u8 bus, u8 s if ( ++bir >= limit ) return 0; return addr + disp + - ((u64)pci_conf_read32(bus, slot, func, base + bir * 4) << 32); + ((u64)pci_conf_read32(seg, bus, slot, func, + base + bir * 4) << 32); } return (addr & PCI_BASE_ADDRESS_MEM_MASK) + disp; } @@ -616,6 +624,7 @@ static int msix_capability_init(struct p u8 bir; void __iomem *base; int idx; + u16 seg = dev->seg; u8 bus = dev->bus; u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); @@ -623,8 +632,8 @@ static int msix_capability_init(struct p ASSERT(spin_is_locked(&pcidevs_lock)); ASSERT(desc); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSIX); - control = pci_conf_read16(bus, slot, func, msix_control_reg(pos)); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); + control = pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos)); msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ /* MSI-X Table Initialization */ @@ -633,7 +642,8 @@ static int msix_capability_init(struct p return -ENOMEM; /* Request & Map MSI-X table region */ - table_offset = pci_conf_read32(bus, slot, func, msix_table_offset_reg(pos)); + table_offset = pci_conf_read32(seg, bus, slot, func, + msix_table_offset_reg(pos)); bir = (u8)(table_offset & PCI_MSIX_BIRMASK); table_offset &= ~PCI_MSIX_BIRMASK; entry_offset = msi->entry_nr * PCI_MSIX_ENTRY_SIZE; @@ -685,7 +695,7 @@ static int msix_capability_init(struct p ASSERT(!dev->msix_used_entries); WARN_ON(msi->table_base != - read_pci_mem_bar(pbus, pslot, pfunc, bir, vf)); + read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf)); dev->msix_nr_entries = nr_entries; dev->msix_table.first = PFN_DOWN(table_paddr); @@ -694,10 +704,10 @@ static int msix_capability_init(struct p WARN_ON(rangeset_overlaps_range(mmio_ro_ranges, dev->msix_table.first, dev->msix_table.last)); - pba_offset = pci_conf_read32(bus, slot, func, + pba_offset = pci_conf_read32(seg, bus, slot, func, msix_pba_offset_reg(pos)); bir = (u8)(pba_offset & PCI_MSIX_BIRMASK); - pba_paddr = read_pci_mem_bar(pbus, pslot, pfunc, bir, vf); + pba_paddr = read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf); WARN_ON(!pba_paddr); pba_paddr += pba_offset & ~PCI_MSIX_BIRMASK; @@ -744,7 +754,7 @@ static int msix_capability_init(struct p *desc = entry; /* Restore MSI-X enabled bits */ - pci_conf_write16(bus, slot, func, msix_control_reg(pos), control); + pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); return 0; } @@ -835,8 +845,9 @@ static int __pci_enable_msix(struct msi_ if ( !pdev ) return -ENODEV; - pos = pci_find_cap_offset(msi->bus, slot, func, PCI_CAP_ID_MSIX); - control = pci_conf_read16(msi->bus, slot, func, msix_control_reg(pos)); + pos = pci_find_cap_offset(msi->seg, msi->bus, slot, func, PCI_CAP_ID_MSIX); + control = pci_conf_read16(msi->seg, msi->bus, slot, func, + msix_control_reg(pos)); nr_entries = multi_msix_capable(control); if (msi->entry_nr >= nr_entries) return -EINVAL; @@ -870,23 +881,24 @@ static void __pci_disable_msix(struct ms { struct pci_dev *dev; int pos; - u16 control; + u16 control, seg; u8 bus, slot, func; dev = entry->dev; + seg = dev->seg; bus = dev->bus; slot = PCI_SLOT(dev->devfn); func = PCI_FUNC(dev->devfn); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSIX); - control = pci_conf_read16(bus, slot, func, msix_control_reg(pos)); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); + control = pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos)); msix_set_enable(dev, 0); BUG_ON(list_empty(&dev->msi_list)); writel(1, entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); - pci_conf_write16(bus, slot, func, msix_control_reg(pos), control); + pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); if ( !--dev->msix_used_entries ) { @@ -995,7 +1007,7 @@ int pci_restore_msi_state(struct pci_dev unsigned int pci_msix_get_table_len(struct pci_dev *pdev) { int pos; - u16 control; + u16 control, seg = pdev->seg; u8 bus, slot, func; unsigned int len; @@ -1003,11 +1015,11 @@ unsigned int pci_msix_get_table_len(stru slot = PCI_SLOT(pdev->devfn); func = PCI_FUNC(pdev->devfn); - pos = pci_find_cap_offset(bus, slot, func, PCI_CAP_ID_MSIX); + pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); if ( !pos ) return 0; - control = pci_conf_read16(bus, slot, func, msix_control_reg(pos)); + control = pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos)); len = msix_table_size(control) * PCI_MSIX_ENTRY_SIZE; return len; --- 2011-09-20.orig/xen/arch/x86/oprofile/op_model_athlon.c 2011-06-16 09:21:02.000000000 +0200 +++ 2011-09-20/xen/arch/x86/oprofile/op_model_athlon.c 2011-08-25 15:13:05.000000000 +0200 @@ -470,7 +470,7 @@ static int __init init_ibs_nmi(void) for (bus = 0; bus < 256; bus++) { for (dev = 0; dev < 32; dev++) { for (func = 0; func < 8; func++) { - id = pci_conf_read32(bus, dev, func, PCI_VENDOR_ID); + id = pci_conf_read32(0, bus, dev, func, PCI_VENDOR_ID); vendor_id = id & 0xffff; dev_id = (id >> 16) & 0xffff; @@ -478,10 +478,10 @@ static int __init init_ibs_nmi(void) if ((vendor_id == PCI_VENDOR_ID_AMD) && (dev_id == PCI_DEVICE_ID_AMD_10H_NB_MISC)) { - pci_conf_write32(bus, dev, func, IBSCTL, + pci_conf_write32(0, bus, dev, func, IBSCTL, IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS); - value = pci_conf_read32(bus, dev, func, IBSCTL); + value = pci_conf_read32(0, bus, dev, func, IBSCTL); if (value != (IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS)) { --- 2011-09-20.orig/xen/arch/x86/x86_32/pci.c 2011-08-08 08:29:50.000000000 +0200 +++ 2011-09-20/xen/arch/x86/x86_32/pci.c 2011-08-25 15:13:05.000000000 +0200 @@ -12,46 +12,61 @@ (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) uint8_t pci_conf_read8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { + if ( seg ) + return ~0; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); return pci_conf_read(PCI_CONF_ADDRESS(bus, dev, func, reg), reg & 3, 1); } uint16_t pci_conf_read16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { + if ( seg ) + return ~0; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); return pci_conf_read(PCI_CONF_ADDRESS(bus, dev, func, reg), reg & 2, 2); } uint32_t pci_conf_read32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { + if ( seg ) + return ~0; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); return pci_conf_read(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4); } void pci_conf_write8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint8_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint8_t data) { + if ( seg ) + return; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), reg & 3, 1, data); } void pci_conf_write16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint16_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint16_t data) { + if ( seg ) + return; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), reg & 2, 2, data); } void pci_conf_write32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint32_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint32_t data) { + if ( seg ) + return; BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4, data); } --- 2011-09-20.orig/xen/arch/x86/x86_64/mmconf-fam10h.c 2011-08-08 08:29:50.000000000 +0200 +++ 2011-09-20/xen/arch/x86/x86_64/mmconf-fam10h.c 2011-08-25 15:13:05.000000000 +0200 @@ -51,7 +51,7 @@ static void __init get_fam10h_pci_mmconf bus = pci_probes[i].bus; slot = pci_probes[i].slot; - id = pci_conf_read32(bus, slot, 0, PCI_VENDOR_ID); + id = pci_conf_read32(0, bus, slot, 0, PCI_VENDOR_ID); vendor = id & 0xffff; device = (id>>16) & 0xffff; @@ -82,12 +82,12 @@ static void __init get_fam10h_pci_mmconf * above 4G */ for (hi_mmio_num = i = 0; i < 8; i++) { - val = pci_conf_read32(bus, slot, 1, 0x80 + (i << 3)); + val = pci_conf_read32(0, bus, slot, 1, 0x80 + (i << 3)); if (!(val & 3)) continue; start = (val & 0xffffff00) << 8; /* 39:16 on 31:8*/ - val = pci_conf_read32(bus, slot, 1, 0x84 + (i << 3)); + val = pci_conf_read32(0, bus, slot, 1, 0x84 + (i << 3)); end = ((val & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/ if (end < tom2) --- 2011-09-20.orig/xen/arch/x86/x86_64/mmconfig-shared.c 2011-08-25 15:06:23.000000000 +0200 +++ 2011-09-20/xen/arch/x86/x86_64/mmconfig-shared.c 2011-08-25 15:13:05.000000000 +0200 @@ -50,7 +50,7 @@ custom_param("mmcfg", parse_mmcfg); static const char __init *pci_mmcfg_e7520(void) { u32 win; - win = pci_conf_read16(0, 0, 0, 0xce); + win = pci_conf_read16(0, 0, 0, 0, 0xce); win = win & 0xf000; if(win == 0x0000 || win == 0xf000) @@ -76,7 +76,7 @@ static const char __init *pci_mmcfg_inte pci_mmcfg_config_num = 1; - pciexbar = pci_conf_read32(0, 0, 0, 0x48); + pciexbar = pci_conf_read32(0, 0, 0, 0, 0x48); /* Enable bit */ if (!(pciexbar & 1)) @@ -201,14 +201,14 @@ static const char __init *pci_mmcfg_nvid u32 l, extcfg; u16 vendor, device; - l = pci_conf_read32(bus, 0, 0, 0); + l = pci_conf_read32(0, bus, 0, 0, 0); vendor = l & 0xffff; device = (l >> 16) & 0xffff; if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) continue; - extcfg = pci_conf_read32(bus, 0, 0, extcfg_regnum); + extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum); if (extcfg & extcfg_enable_mask) i++; @@ -227,14 +227,14 @@ static const char __init *pci_mmcfg_nvid u16 vendor, device; int size_index; - l = pci_conf_read32(bus, 0, 0, 0); + l = pci_conf_read32(0, bus, 0, 0, 0); vendor = l & 0xffff; device = (l >> 16) & 0xffff; if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) continue; - extcfg = pci_conf_read32(bus, 0, 0, extcfg_regnum); + extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum); if (!(extcfg & extcfg_enable_mask)) continue; @@ -300,7 +300,7 @@ static int __init pci_mmcfg_check_hostbr for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { bus = pci_mmcfg_probes[i].bus; devfn = pci_mmcfg_probes[i].devfn; - l = pci_conf_read32(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); + l = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); vendor = l & 0xffff; device = (l >> 16) & 0xffff; @@ -473,7 +473,7 @@ int pci_find_ext_capability(int seg, int int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ int pos = 0x100; - header = pci_conf_read32(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); + header = pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); /* * If we have no capabilities, this is indicated by cap ID, @@ -488,7 +488,7 @@ int pci_find_ext_capability(int seg, int pos = PCI_EXT_CAP_NEXT(header); if ( pos < 0x100 ) break; - header = pci_conf_read32(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); + header = pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); } return 0; } --- 2011-09-20.orig/xen/arch/x86/x86_64/pci.c 2009-10-07 13:31:36.000000000 +0200 +++ 2011-09-20/xen/arch/x86/x86_64/pci.c 2011-08-25 15:13:05.000000000 +0200 @@ -12,13 +12,14 @@ (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) uint8_t pci_conf_read8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { u32 value; - if ( reg > 255 ) + if ( seg || reg > 255 ) { - pci_mmcfg_read(0, bus, PCI_DEVFN(dev, func), reg, 1, &value); + pci_mmcfg_read(seg, bus, PCI_DEVFN(dev, func), reg, 1, &value); return value; } else @@ -29,13 +30,14 @@ uint8_t pci_conf_read8( } uint16_t pci_conf_read16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { u32 value; - if ( reg > 255 ) + if ( seg || reg > 255 ) { - pci_mmcfg_read(0, bus, PCI_DEVFN(dev, func), reg, 2, &value); + pci_mmcfg_read(seg, bus, PCI_DEVFN(dev, func), reg, 2, &value); return value; } else @@ -46,13 +48,14 @@ uint16_t pci_conf_read16( } uint32_t pci_conf_read32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg) { u32 value; - if ( reg > 255 ) + if ( seg || reg > 255 ) { - pci_mmcfg_read(0, bus, PCI_DEVFN(dev, func), reg, 4, &value); + pci_mmcfg_read(seg, bus, PCI_DEVFN(dev, func), reg, 4, &value); return value; } else @@ -63,11 +66,11 @@ uint32_t pci_conf_read32( } void pci_conf_write8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint8_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint8_t data) { - if ( reg > 255 ) - pci_mmcfg_write(0, bus, PCI_DEVFN(dev, func), reg, 1, data); + if ( seg || reg > 255 ) + pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 1, data); else { BUG_ON((bus > 255) || (dev > 31) || (func > 7)); @@ -76,11 +79,11 @@ void pci_conf_write8( } void pci_conf_write16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint16_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint16_t data) { - if ( reg > 255 ) - pci_mmcfg_write(0, bus, PCI_DEVFN(dev, func), reg, 2, data); + if ( seg || reg > 255 ) + pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 2, data); else { BUG_ON((bus > 255) || (dev > 31) || (func > 7)); @@ -89,11 +92,11 @@ void pci_conf_write16( } void pci_conf_write32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint32_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint32_t data) { - if ( reg > 255 ) - pci_mmcfg_write(0, bus, PCI_DEVFN(dev, func), reg, 4, data); + if ( seg || reg > 255 ) + pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 4, data); else { BUG_ON((bus > 255) || (dev > 31) || (func > 7)); --- 2011-09-20.orig/xen/drivers/acpi/reboot.c 2010-12-23 08:18:08.000000000 +0100 +++ 2011-09-20/xen/drivers/acpi/reboot.c 2011-08-25 15:13:05.000000000 +0200 @@ -24,7 +24,7 @@ void acpi_reboot(void) case ACPI_ADR_SPACE_PCI_CONFIG: printk("Resetting with ACPI PCI RESET_REG.\n"); /* Write the value that resets us. */ - pci_conf_write8(0, + pci_conf_write8(0, 0, (rr->address >> 32) & 31, (rr->address >> 16) & 7, (rr->address & 255), --- 2011-09-20.orig/xen/drivers/char/ns16550.c 2011-09-05 09:12:30.000000000 +0200 +++ 2011-09-20/xen/drivers/char/ns16550.c 2011-09-20 16:06:57.000000000 +0200 @@ -212,12 +212,12 @@ static void pci_serial_early_init(struct return; if ( uart->pb_bdf_enable ) - pci_conf_write16(uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], + pci_conf_write16(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], 0x1c, (uart->io_base & 0xF000) | ((uart->io_base & 0xF000) >> 8)); - pci_conf_write32(uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], 0x10, uart->io_base | 0x1); - pci_conf_write16(uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], 0x4, 0x1); } @@ -329,10 +329,10 @@ static void ns16550_suspend(struct seria if ( uart->bar ) { uart->bar = pci_conf_read32( - uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], + 0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], PCI_BASE_ADDRESS_0 + uart->bar_idx*4); uart->cr = pci_conf_read32( - uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], + 0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], PCI_COMMAND); } } @@ -346,9 +346,9 @@ static void ns16550_resume(struct serial if ( uart->bar ) { - pci_conf_write32(uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], + pci_conf_write32(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); - pci_conf_write32(uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], + pci_conf_write32(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], PCI_COMMAND, uart->cr); } } @@ -467,19 +467,20 @@ pci_uart_config (struct ns16550 *uart, i { for ( f = 0; f < 0x8; f++ ) { - class = pci_conf_read16(b, d, f, PCI_CLASS_DEVICE); + class = pci_conf_read16(0, b, d, f, PCI_CLASS_DEVICE); if ( class != 0x700 ) continue; - bar = pci_conf_read32(b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4); + bar = pci_conf_read32(0, b, d, f, + PCI_BASE_ADDRESS_0 + bar_idx*4); /* Not IO */ if ( !(bar & 1) ) continue; - pci_conf_write32(b, d, f, PCI_BASE_ADDRESS_0, ~0u); - len = pci_conf_read32(b, d, f, PCI_BASE_ADDRESS_0); - pci_conf_write32(b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4, bar); + pci_conf_write32(0, b, d, f, PCI_BASE_ADDRESS_0, ~0u); + len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0); + pci_conf_write32(0, b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4, bar); /* Not 8 bytes */ if ( (len & 0xffff) != 0xfff9 ) --- 2011-09-20.orig/xen/drivers/passthrough/amd/iommu_detect.c 2011-08-25 15:06:47.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/amd/iommu_detect.c 2011-08-25 15:13:05.000000000 +0200 @@ -35,14 +35,14 @@ static int __init get_iommu_msi_capabili u16 control; int count = 0; - cap_ptr = pci_conf_read8(bus, dev, func, + cap_ptr = pci_conf_read8(seg, bus, dev, func, PCI_CAPABILITY_LIST); while ( cap_ptr >= PCI_MIN_CAP_OFFSET && count < PCI_MAX_CAP_BLOCKS ) { cap_ptr &= PCI_CAP_PTR_MASK; - cap_header = pci_conf_read32(bus, dev, func, cap_ptr); + cap_header = pci_conf_read32(seg, bus, dev, func, cap_ptr); cap_id = get_field_from_reg_u32(cap_header, PCI_CAP_ID_MASK, PCI_CAP_ID_SHIFT); @@ -60,7 +60,7 @@ static int __init get_iommu_msi_capabili return -ENODEV; AMD_IOMMU_DEBUG("Found MSI capability block \n"); - control = pci_conf_read16(bus, dev, func, + control = pci_conf_read16(seg, bus, dev, func, iommu->msi_cap + PCI_MSI_FLAGS); iommu->maskbit = control & PCI_MSI_FLAGS_MASKBIT; return 0; @@ -71,18 +71,18 @@ static int __init get_iommu_capabilities { u32 cap_header, cap_range, misc_info; - cap_header = pci_conf_read32(bus, dev, func, cap_ptr); + cap_header = pci_conf_read32(seg, bus, dev, func, cap_ptr); iommu->revision = get_field_from_reg_u32( cap_header, PCI_CAP_REV_MASK, PCI_CAP_REV_SHIFT); iommu->pte_not_present_cached = get_field_from_reg_u32( cap_header, PCI_CAP_NP_CACHE_MASK, PCI_CAP_NP_CACHE_SHIFT); - cap_range = pci_conf_read32(bus, dev, func, + cap_range = pci_conf_read32(seg, bus, dev, func, cap_ptr + PCI_CAP_RANGE_OFFSET); iommu->unit_id = get_field_from_reg_u32( cap_range, PCI_CAP_UNIT_ID_MASK, PCI_CAP_UNIT_ID_SHIFT); - misc_info = pci_conf_read32(bus, dev, func, + misc_info = pci_conf_read32(seg, bus, dev, func, cap_ptr + PCI_MISC_INFO_OFFSET); iommu->msi_number = get_field_from_reg_u32( misc_info, PCI_CAP_MSI_NUMBER_MASK, PCI_CAP_MSI_NUMBER_SHIFT); --- 2011-09-20.orig/xen/drivers/passthrough/amd/iommu_init.c 2011-08-25 15:06:47.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/amd/iommu_init.c 2011-08-25 15:19:59.000000000 +0200 @@ -269,7 +269,7 @@ static void set_iommu_event_log_control( writel(entry, iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET); } -static void parse_event_log_entry(u32 entry[]); +static void parse_event_log_entry(struct amd_iommu *, u32 entry[]); static int amd_iommu_read_event_log(struct amd_iommu *iommu) { @@ -290,7 +290,7 @@ static int amd_iommu_read_event_log(stru (iommu->event_log_head * IOMMU_EVENT_LOG_ENTRY_SIZE)); - parse_event_log_entry(event_log); + parse_event_log_entry(iommu, event_log); if ( ++iommu->event_log_head == iommu->event_log.entries ) iommu->event_log_head = 0; @@ -351,6 +351,7 @@ static void iommu_msi_set_affinity(unsig struct amd_iommu *iommu = irq_to_iommu[irq]; struct irq_desc *desc = irq_to_desc(irq); struct irq_cfg *cfg = desc->chip_data; + u16 seg = iommu->seg; u8 bus = (iommu->bdf >> 8) & 0xff; u8 dev = PCI_SLOT(iommu->bdf & 0xff); u8 func = PCI_FUNC(iommu->bdf & 0xff); @@ -379,11 +380,11 @@ static void iommu_msi_set_affinity(unsig MSI_ADDR_REDIRECTION_LOWPRI; msg.address_lo |= MSI_ADDR_DEST_ID(dest & 0xff); - pci_conf_write32(bus, dev, func, + pci_conf_write32(seg, bus, dev, func, iommu->msi_cap + PCI_MSI_DATA_64, msg.data); - pci_conf_write32(bus, dev, func, + pci_conf_write32(seg, bus, dev, func, iommu->msi_cap + PCI_MSI_ADDRESS_LO, msg.address_lo); - pci_conf_write32(bus, dev, func, + pci_conf_write32(seg, bus, dev, func, iommu->msi_cap + PCI_MSI_ADDRESS_HI, msg.address_hi); } @@ -395,12 +396,12 @@ static void amd_iommu_msi_enable(struct int dev = PCI_SLOT(iommu->bdf & 0xff); int func = PCI_FUNC(iommu->bdf & 0xff); - control = pci_conf_read16(bus, dev, func, + control = pci_conf_read16(iommu->seg, bus, dev, func, iommu->msi_cap + PCI_MSI_FLAGS); control &= ~(1); if ( flag ) control |= flag; - pci_conf_write16(bus, dev, func, + pci_conf_write16(iommu->seg, bus, dev, func, iommu->msi_cap + PCI_MSI_FLAGS, control); } @@ -459,7 +460,7 @@ static hw_irq_controller iommu_msi_type .set_affinity = iommu_msi_set_affinity, }; -static void parse_event_log_entry(u32 entry[]) +static void parse_event_log_entry(struct amd_iommu *iommu, u32 entry[]) { u16 domain_id, device_id, bdf, cword; u32 code; @@ -500,11 +501,12 @@ static void parse_event_log_entry(u32 en /* Tell the device to stop DMAing; we can't rely on the guest to * control it for us. */ for ( bdf = 0; bdf < ivrs_bdf_entries; bdf++ ) - if ( get_dma_requestor_id(bdf) == device_id ) + if ( get_dma_requestor_id(iommu->seg, bdf) == device_id ) { - cword = pci_conf_read16(PCI_BUS(bdf), PCI_SLOT(bdf), - PCI_FUNC(bdf), PCI_COMMAND); - pci_conf_write16(PCI_BUS(bdf), PCI_SLOT(bdf), + cword = pci_conf_read16(iommu->seg, PCI_BUS(bdf), + PCI_SLOT(bdf), PCI_FUNC(bdf), + PCI_COMMAND); + pci_conf_write16(iommu->seg, PCI_BUS(bdf), PCI_SLOT(bdf), PCI_FUNC(bdf), PCI_COMMAND, cword & ~PCI_COMMAND_MASTER); } --- 2011-09-20.orig/xen/drivers/passthrough/pci.c 2011-08-25 15:12:12.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/pci.c 2011-08-25 15:13:05.000000000 +0200 @@ -214,8 +214,8 @@ void pci_enable_acs(struct pci_dev *pdev if (!pos) return; - cap = pci_conf_read16(bus, dev, func, pos + PCI_ACS_CAP); - ctrl = pci_conf_read16(bus, dev, func, pos + PCI_ACS_CTRL); + cap = pci_conf_read16(seg, bus, dev, func, pos + PCI_ACS_CAP); + ctrl = pci_conf_read16(seg, bus, dev, func, pos + PCI_ACS_CTRL); /* Source Validation */ ctrl |= (cap & PCI_ACS_SV); @@ -229,7 +229,7 @@ void pci_enable_acs(struct pci_dev *pdev /* Upstream Forwarding */ ctrl |= (cap & PCI_ACS_UF); - pci_conf_write16(bus, dev, func, pos + PCI_ACS_CTRL, ctrl); + pci_conf_write16(seg, bus, dev, func, pos + PCI_ACS_CTRL, ctrl); } int pci_add_device(u16 seg, u8 bus, u8 devfn, const struct pci_dev_info *info) @@ -273,7 +273,7 @@ int pci_add_device(u16 seg, u8 bus, u8 d { unsigned int pos = pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_SRIOV); - u16 ctrl = pci_conf_read16(bus, slot, func, pos + PCI_SRIOV_CTRL); + u16 ctrl = pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV_CTRL); if ( !pos ) /* Nothing */; @@ -285,7 +285,7 @@ int pci_add_device(u16 seg, u8 bus, u8 d for ( i = 0; i < PCI_SRIOV_NUM_BARS; ++i ) { unsigned int idx = pos + PCI_SRIOV_BAR + i * 4; - u32 bar = pci_conf_read32(bus, slot, func, idx); + u32 bar = pci_conf_read32(seg, bus, slot, func, idx); u32 hi = 0; if ( (bar & PCI_BASE_ADDRESS_SPACE) == @@ -297,7 +297,7 @@ int pci_add_device(u16 seg, u8 bus, u8 d seg, bus, slot, func, i); continue; } - pci_conf_write32(bus, slot, func, idx, ~0); + pci_conf_write32(seg, bus, slot, func, idx, ~0); if ( (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64 ) { @@ -309,21 +309,22 @@ int pci_add_device(u16 seg, u8 bus, u8 d seg, bus, slot, func); break; } - hi = pci_conf_read32(bus, slot, func, idx + 4); - pci_conf_write32(bus, slot, func, idx + 4, ~0); + hi = pci_conf_read32(seg, bus, slot, func, idx + 4); + pci_conf_write32(seg, bus, slot, func, idx + 4, ~0); } - pdev->vf_rlen[i] = pci_conf_read32(bus, slot, func, idx) & + pdev->vf_rlen[i] = pci_conf_read32(seg, bus, slot, func, idx) & PCI_BASE_ADDRESS_MEM_MASK; if ( (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64 ) { - pdev->vf_rlen[i] |= (u64)pci_conf_read32(bus, slot, func, + pdev->vf_rlen[i] |= (u64)pci_conf_read32(seg, bus, + slot, func, idx + 4) << 32; - pci_conf_write32(bus, slot, func, idx + 4, hi); + pci_conf_write32(seg, bus, slot, func, idx + 4, hi); } else if ( pdev->vf_rlen[i] ) pdev->vf_rlen[i] |= (u64)~0 << 32; - pci_conf_write32(bus, slot, func, idx, bar); + pci_conf_write32(seg, bus, slot, func, idx, bar); pdev->vf_rlen[i] = -pdev->vf_rlen[i]; if ( (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64 ) @@ -458,23 +459,24 @@ int pdev_type(u16 seg, u8 bus, u8 devfn) int pos; u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn); - class_device = pci_conf_read16(bus, d, f, PCI_CLASS_DEVICE); + class_device = pci_conf_read16(seg, bus, d, f, PCI_CLASS_DEVICE); if ( class_device == PCI_CLASS_BRIDGE_PCI ) { - pos = pci_find_next_cap(bus, devfn, + pos = pci_find_next_cap(seg, bus, devfn, PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP); if ( !pos ) return DEV_TYPE_LEGACY_PCI_BRIDGE; - creg = pci_conf_read16(bus, d, f, pos + PCI_EXP_FLAGS); + creg = pci_conf_read16(seg, bus, d, f, pos + PCI_EXP_FLAGS); return ((creg & PCI_EXP_FLAGS_TYPE) >> 4) == PCI_EXP_TYPE_PCI_BRIDGE ? DEV_TYPE_PCIe2PCI_BRIDGE : DEV_TYPE_PCIe_BRIDGE; } - status = pci_conf_read16(bus, d, f, PCI_STATUS); + status = pci_conf_read16(seg, bus, d, f, PCI_STATUS); if ( !(status & PCI_STATUS_CAP_LIST) ) return DEV_TYPE_PCI; - if ( pci_find_next_cap(bus, devfn, PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP) ) + if ( pci_find_next_cap(seg, bus, devfn, PCI_CAPABILITY_LIST, + PCI_CAP_ID_EXP) ) return DEV_TYPE_PCIe_ENDPOINT; return DEV_TYPE_PCI; @@ -527,7 +529,7 @@ int __init pci_device_detect(u16 seg, u8 { u32 vendor; - vendor = pci_conf_read32(bus, dev, func, PCI_VENDOR_ID); + vendor = pci_conf_read32(seg, bus, dev, func, PCI_VENDOR_ID); /* some broken boards return 0 or ~0 if a slot is empty: */ if ( (vendor == 0xffffffff) || (vendor == 0x00000000) || (vendor == 0x0000ffff) || (vendor == 0xffff0000) ) @@ -571,9 +573,9 @@ static int __init _scan_pci_devices(stru case DEV_TYPE_PCIe2PCI_BRIDGE: case DEV_TYPE_LEGACY_PCI_BRIDGE: - sec_bus = pci_conf_read8(bus, dev, func, + sec_bus = pci_conf_read8(pseg->nr, bus, dev, func, PCI_SECONDARY_BUS); - sub_bus = pci_conf_read8(bus, dev, func, + sub_bus = pci_conf_read8(pseg->nr, bus, dev, func, PCI_SUBORDINATE_BUS); spin_lock(&pseg->bus2bridge_lock); @@ -597,7 +599,7 @@ static int __init _scan_pci_devices(stru return -EINVAL; } - if ( !func && !(pci_conf_read8(bus, dev, func, + if ( !func && !(pci_conf_read8(pseg->nr, bus, dev, func, PCI_HEADER_TYPE) & 0x80) ) break; } @@ -667,7 +669,7 @@ static int _disconnect_pci_devices(struc struct pci_dev *pdev; list_for_each_entry ( pdev, &pseg->alldevs_list, alldevs_list ) - pci_conf_write16(pdev->bus, PCI_SLOT(pdev->devfn), + pci_conf_write16(pseg->nr, pdev->bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), PCI_COMMAND, 0); return 0; --- 2011-09-20.orig/xen/drivers/passthrough/vtd/dmar.c 2011-08-25 15:12:12.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/vtd/dmar.c 2011-08-25 15:13:05.000000000 +0200 @@ -307,17 +307,18 @@ static int __init acpi_parse_dev_scope( while ( --depth > 0 ) { - bus = pci_conf_read8(bus, path->dev, path->fn, PCI_SECONDARY_BUS); + bus = pci_conf_read8(seg, bus, path->dev, path->fn, + PCI_SECONDARY_BUS); path++; } switch ( acpi_scope->dev_type ) { case ACPI_DEV_P2PBRIDGE: - sec_bus = pci_conf_read8( - bus, path->dev, path->fn, PCI_SECONDARY_BUS); - sub_bus = pci_conf_read8( - bus, path->dev, path->fn, PCI_SUBORDINATE_BUS); + sec_bus = pci_conf_read8(seg, bus, path->dev, path->fn, + PCI_SECONDARY_BUS); + sub_bus = pci_conf_read8(seg, bus, path->dev, path->fn, + PCI_SUBORDINATE_BUS); if ( iommu_verbose ) dprintk(VTDPREFIX, " bridge: %04x:%02x:%02x.%u start=%x sec=%x sub=%x\n", --- 2011-09-20.orig/xen/drivers/passthrough/vtd/iommu.c 2011-09-20 16:06:42.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/vtd/iommu.c 2011-09-20 16:06:48.000000000 +0200 @@ -941,11 +941,12 @@ static void iommu_page_fault(int irq, vo /* Tell the device to stop DMAing; we can't rely on the guest to * control it for us. */ - cword = pci_conf_read16(PCI_BUS(source_id), PCI_SLOT(source_id), + cword = pci_conf_read16(iommu->intel->drhd->segment, + PCI_BUS(source_id), PCI_SLOT(source_id), PCI_FUNC(source_id), PCI_COMMAND); - pci_conf_write16(PCI_BUS(source_id), PCI_SLOT(source_id), - PCI_FUNC(source_id), PCI_COMMAND, - cword & ~PCI_COMMAND_MASTER); + pci_conf_write16(iommu->intel->drhd->segment, PCI_BUS(source_id), + PCI_SLOT(source_id), PCI_FUNC(source_id), + PCI_COMMAND, cword & ~PCI_COMMAND_MASTER); fault_index++; if ( fault_index > cap_num_fault_regs(iommu->cap) ) --- 2011-09-20.orig/xen/drivers/passthrough/vtd/quirks.c 2011-08-25 15:06:35.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/vtd/quirks.c 2011-08-25 15:13:05.000000000 +0200 @@ -70,7 +70,7 @@ int is_igd_vt_enabled_quirk(void) return 1; /* integrated graphics on Intel platforms is located at 0:2.0 */ - ggc = pci_conf_read16(0, IGD_DEV, 0, GGC); + ggc = pci_conf_read16(0, 0, IGD_DEV, 0, GGC); return ( ggc & GGC_MEMORY_VT_ENABLED ? 1 : 0 ); } @@ -84,12 +84,12 @@ static void __init cantiga_b3_errata_ini u16 vid; u8 did_hi, rid; - vid = pci_conf_read16(0, IGD_DEV, 0, 0); + vid = pci_conf_read16(0, 0, IGD_DEV, 0, 0); if ( vid != 0x8086 ) return; - did_hi = pci_conf_read8(0, IGD_DEV, 0, 3); - rid = pci_conf_read8(0, IGD_DEV, 0, 8); + did_hi = pci_conf_read8(0, 0, IGD_DEV, 0, 3); + rid = pci_conf_read8(0, 0, IGD_DEV, 0, 8); if ( (did_hi == 0x2A) && (rid == 0x7) ) is_cantiga_b3 = 1; @@ -125,8 +125,8 @@ static void __init map_igd_reg(void) return; /* get IGD mmio address in PCI BAR */ - igd_mmio = ((u64)pci_conf_read32(0, IGD_DEV, 0, 0x14) << 32) + - pci_conf_read32(0, IGD_DEV, 0, 0x10); + igd_mmio = ((u64)pci_conf_read32(0, 0, IGD_DEV, 0, 0x14) << 32) + + pci_conf_read32(0, 0, IGD_DEV, 0, 0x10); /* offset of IGD regster we want to access is in 0x2000 range */ igd_reg = (igd_mmio & IGD_BAR_MASK) + 0x2000; @@ -251,8 +251,8 @@ void vtd_ops_postamble_quirk(struct iomm /* initialize platform identification flags */ void __init platform_quirks_init(void) { - ioh_id = pci_conf_read32(0, IOH_DEV, 0, 0); - igd_id = pci_conf_read32(0, IGD_DEV, 0, 0); + ioh_id = pci_conf_read32(0, 0, IOH_DEV, 0, 0); + igd_id = pci_conf_read32(0, 0, IGD_DEV, 0, 0); /* Mobile 4 Series Chipset neglects to set RWBF capability. */ if ( ioh_id == 0x2a408086 ) @@ -302,15 +302,15 @@ void me_wifi_quirk(struct domain *domain { u32 id; - id = pci_conf_read32(0, 0, 0, 0); + id = pci_conf_read32(0, 0, 0, 0, 0); if ( IS_CTG(id) ) { /* quit if ME does not exist */ - if ( pci_conf_read32(0, 3, 0, 0) == 0xffffffff ) + if ( pci_conf_read32(0, 0, 3, 0, 0) == 0xffffffff ) return; /* if device is WLAN device, map ME phantom device 0:3.7 */ - id = pci_conf_read32(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); + id = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); switch (id) { case 0x42328086: @@ -330,11 +330,11 @@ void me_wifi_quirk(struct domain *domain else if ( IS_ILK(id) || IS_CPT(id) ) { /* quit if ME does not exist */ - if ( pci_conf_read32(0, 22, 0, 0) == 0xffffffff ) + if ( pci_conf_read32(0, 0, 22, 0, 0) == 0xffffffff ) return; /* if device is WLAN device, map ME phantom device 0:22.7 */ - id = pci_conf_read32(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); + id = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); switch (id) { case 0x00878086: /* Kilmer Peak */ @@ -364,16 +364,17 @@ void me_wifi_quirk(struct domain *domain void __init pci_vtd_quirk(struct pci_dev *pdev) { #ifdef CONFIG_X86_64 + int seg = pdev->seg; int bus = pdev->bus; int dev = PCI_SLOT(pdev->devfn); int func = PCI_FUNC(pdev->devfn); int id, val; - id = pci_conf_read32(bus, dev, func, 0); + id = pci_conf_read32(seg, bus, dev, func, 0); if ( id == 0x342e8086 || id == 0x3c288086 ) { - val = pci_conf_read32(bus, dev, func, 0x1AC); - pci_conf_write32(bus, dev, func, 0x1AC, val | (1 << 31)); + val = pci_conf_read32(seg, bus, dev, func, 0x1AC); + pci_conf_write32(seg, bus, dev, func, 0x1AC, val | (1 << 31)); } #endif } --- 2011-09-20.orig/xen/drivers/passthrough/vtd/utils.c 2011-08-25 15:06:43.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/vtd/utils.c 2011-08-25 15:13:05.000000000 +0200 @@ -34,7 +34,7 @@ int is_usb_device(u16 seg, u8 bus, u8 devfn) { - u16 class = pci_conf_read16(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + u16 class = pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), PCI_CLASS_DEVICE); return (class == 0xc03); } --- 2011-09-20.orig/xen/drivers/passthrough/vtd/x86/ats.c 2011-08-25 15:06:43.000000000 +0200 +++ 2011-09-20/xen/drivers/passthrough/vtd/x86/ats.c 2011-08-25 15:13:05.000000000 +0200 @@ -135,8 +135,7 @@ int enable_ats_device(int seg, int bus, "%04x:%02x:%02x.%u: ATS capability found\n", seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); - /* BUGBUG: add back seg when multi-seg platform support is enabled */ - value = pci_conf_read16(bus, PCI_SLOT(devfn), + value = pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + ATS_REG_CTL); if ( value & ATS_ENABLE ) { @@ -157,7 +156,7 @@ int enable_ats_device(int seg, int bus, if ( !(value & ATS_ENABLE) ) { value |= ATS_ENABLE; - pci_conf_write16(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + pci_conf_write16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + ATS_REG_CTL, value); } @@ -166,7 +165,7 @@ int enable_ats_device(int seg, int bus, pdev->seg = seg; pdev->bus = bus; pdev->devfn = devfn; - value = pci_conf_read16(bus, PCI_SLOT(devfn), + value = pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + ATS_REG_CAP); pdev->ats_queue_depth = value & ATS_QUEUE_DEPTH_MASK; list_add(&pdev->list, &ats_devices); @@ -190,11 +189,10 @@ void disable_ats_device(int seg, int bus pos = pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); - /* BUGBUG: add back seg when multi-seg platform support is enabled */ - value = pci_conf_read16(bus, PCI_SLOT(devfn), + value = pci_conf_read16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + ATS_REG_CTL); value &= ~ATS_ENABLE; - pci_conf_write16(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + pci_conf_write16(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + ATS_REG_CTL, value); list_for_each_entry ( pdev, &ats_devices, list ) --- 2011-09-20.orig/xen/drivers/pci/pci.c 2008-10-13 13:36:27.000000000 +0200 +++ 2011-09-20/xen/drivers/pci/pci.c 2011-08-25 15:13:05.000000000 +0200 @@ -7,25 +7,25 @@ #include #include -int pci_find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap) +int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap) { u8 id; int max_cap = 48; u8 pos = PCI_CAPABILITY_LIST; u16 status; - status = pci_conf_read16(bus, dev, func, PCI_STATUS); + status = pci_conf_read16(seg, bus, dev, func, PCI_STATUS); if ( (status & PCI_STATUS_CAP_LIST) == 0 ) return 0; while ( max_cap-- ) { - pos = pci_conf_read8(bus, dev, func, pos); + pos = pci_conf_read8(seg, bus, dev, func, pos); if ( pos < 0x40 ) break; pos &= ~3; - id = pci_conf_read8(bus, dev, func, pos + PCI_CAP_LIST_ID); + id = pci_conf_read8(seg, bus, dev, func, pos + PCI_CAP_LIST_ID); if ( id == 0xff ) break; @@ -38,19 +38,19 @@ int pci_find_cap_offset(u8 bus, u8 dev, return 0; } -int pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap) +int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) { u8 id; int ttl = 48; while ( ttl-- ) { - pos = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); + pos = pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); if ( pos < 0x40 ) break; pos &= ~3; - id = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + id = pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos + PCI_CAP_LIST_ID); if ( id == 0xff ) --- 2011-09-20.orig/xen/include/xen/pci.h 2011-08-25 15:12:12.000000000 +0200 +++ 2011-09-20/xen/include/xen/pci.h 2011-08-25 15:13:05.000000000 +0200 @@ -102,28 +102,31 @@ struct pci_dev *pci_get_pdev_by_domain( void disconnect_pci_devices(void); uint8_t pci_conf_read8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg); uint16_t pci_conf_read16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg); uint32_t pci_conf_read32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg); void pci_conf_write8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint8_t data); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint8_t data); void pci_conf_write16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint16_t data); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint16_t data); void pci_conf_write32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg, - uint32_t data); + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, + unsigned int reg, uint32_t data); uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes); void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t data); int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value); int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); -int pci_find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap); -int pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap); +int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); +int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap); int pci_find_ext_capability(int seg, int bus, int devfn, int cap); struct pirq;