x86: Intel CPU family update

... according to revision 49 of the Intel SDM.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
Intel: Clarification is needed that I correctly resolved the ambiguity
the manual has for 06_4D: Table 35-1 lists this among the Silvermont
ones and uses 06_4E for Future Generation Intel Core; section 35.1 and
table 35-24, however, use 06_4D throughout. My take is that the latter
is what is wrong.

--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -139,6 +139,9 @@ static void do_get_hw_residencies(void *
     case 0x3F:
     case 0x45:
     case 0x46:
+    /* future */
+    case 0x3D:
+    case 0x4E:
         GET_PC2_RES(hw_res->pc2);
         GET_CC7_RES(hw_res->cc7);
         /* fall through */
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1966,10 +1966,14 @@ static const struct lbr_info *last_branc
         case 58: case 62:
         /* Haswell */
         case 60: case 63: case 69: case 70:
+        /* future */
+        case 61: case 78:
             return nh_lbr;
             break;
         /* Atom */
-        case 28:
+        case 28: case 38: case 39: case 53: case 54:
+        /* Silvermont */
+        case 55: case 74: case 77: case 90: case 93:
             return at_lbr;
             break;
         }
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -916,6 +916,10 @@ int vmx_vpmu_initialise(struct vcpu *v, 
         case 0x3f:
         case 0x45:
         case 0x46:
+
+        /* future: */
+        case 0x3d:
+        case 0x4e:
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;