x86/HVM: fix miscellaneous aspects of x2APIC emulation - generate #GP on invalid APIC base MSR transitions - fail reads from the EOI and self-IPI registers (which are write-only) - handle self-IPI writes and the ICR2 half of ICR writes largely in hvm_x2apic_msr_write() and (for self-IPI only) vlapic_apicv_write() - don't permit MMIO-based access in x2APIC mode - filter writes to read-only registers in hvm_x2apic_msr_write(), allowing conditionals to be dropped from vlapic_reg_write() - don't ignore upper half of MSR-based write to ESR being non-zero - VMX's EXIT_REASON_APIC_WRITE must not result in #GP (this exit being trap-like, this exception would get raised on the wrong RIP) - make hvm_x2apic_msr_read() produce X86EMUL_* return codes just like hvm_x2apic_msr_write() does (benign to the only caller) Signed-off-by: Jan Beulich --- v3: Also handle APIC_EOI in hvm_x2apic_msr_read() as pointed out by Andrew. Filter MMIO-based accesses in vlapic_range() when in x2APIC mode. Move x2APIC special casing from vlapic_reg_write() to hvm_x2apic_msr_write(). Don't open-code vlapic_x2apic_mode(). v2: Split from main patch. --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4499,7 +4499,8 @@ int hvm_msr_write_intercept(unsigned int break; case MSR_IA32_APICBASE: - vlapic_msr_set(vcpu_vlapic(v), msr_content); + if ( !vlapic_msr_set(vcpu_vlapic(v), msr_content) ) + goto gp_fault; break; case MSR_IA32_TSC_DEADLINE: --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -588,7 +588,7 @@ int hvm_x2apic_msr_read(struct vcpu *v, uint32_t low, high = 0, offset = (msr - MSR_IA32_APICBASE_MSR) << 4; if ( !vlapic_x2apic_mode(vlapic) ) - return 1; + return X86EMUL_UNHANDLEABLE; vlapic_read_aligned(vlapic, offset, &low); switch ( offset ) @@ -601,12 +601,15 @@ int hvm_x2apic_msr_read(struct vcpu *v, vlapic_read_aligned(vlapic, APIC_ICR2, &high); break; + case APIC_EOI: case APIC_ICR2: - return 1; + case APIC_SELF_IPI: + return X86EMUL_UNHANDLEABLE; } *msr_content = (((uint64_t)high) << 32) | low; - return 0; + + return X86EMUL_OKAY; } static void vlapic_pt_cb(struct vcpu *v, void *data) @@ -630,10 +633,7 @@ static int vlapic_reg_write(struct vcpu switch ( offset ) { case APIC_ID: - if ( !vlapic_x2apic_mode(vlapic) ) - vlapic_set_reg(vlapic, APIC_ID, val); - else - rc = X86EMUL_UNHANDLEABLE; + vlapic_set_reg(vlapic, APIC_ID, val); break; case APIC_TASKPRI: @@ -645,17 +645,11 @@ static int vlapic_reg_write(struct vcpu break; case APIC_LDR: - if ( !vlapic_x2apic_mode(vlapic) ) - vlapic_set_reg(vlapic, APIC_LDR, val & APIC_LDR_MASK); - else - rc = X86EMUL_UNHANDLEABLE; + vlapic_set_reg(vlapic, APIC_LDR, val & APIC_LDR_MASK); break; case APIC_DFR: - if ( !vlapic_x2apic_mode(vlapic) ) - vlapic_set_reg(vlapic, APIC_DFR, val | 0x0FFFFFFF); - else - rc = X86EMUL_UNHANDLEABLE; + vlapic_set_reg(vlapic, APIC_DFR, val | 0x0FFFFFFF); break; case APIC_SPIV: @@ -682,21 +676,6 @@ static int vlapic_reg_write(struct vcpu } break; - case APIC_ESR: - if ( vlapic_x2apic_mode(vlapic) && (val != 0) ) - { - gdprintk(XENLOG_ERR, "Local APIC write ESR with non-zero %lx\n", - val); - rc = X86EMUL_UNHANDLEABLE; - } - break; - - case APIC_SELF_IPI: - rc = vlapic_x2apic_mode(vlapic) - ? vlapic_reg_write(v, APIC_ICR, 0x40000 | (val & 0xff)) - : X86EMUL_UNHANDLEABLE; - break; - case APIC_ICR: val &= ~(1 << 12); /* always clear the pending bit */ vlapic_ipi(vlapic, val, vlapic_get_reg(vlapic, APIC_ICR2)); @@ -704,9 +683,7 @@ static int vlapic_reg_write(struct vcpu break; case APIC_ICR2: - if ( !vlapic_x2apic_mode(vlapic) ) - val &= 0xff000000; - vlapic_set_reg(vlapic, APIC_ICR2, val); + vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000); break; case APIC_LVTT: /* LVT Timer Reg */ @@ -851,8 +828,16 @@ static int vlapic_write(struct vcpu *v, int vlapic_apicv_write(struct vcpu *v, unsigned int offset) { - uint32_t val = vlapic_get_reg(vcpu_vlapic(v), offset); - return vlapic_reg_write(v, offset, val); + struct vlapic *vlapic = vcpu_vlapic(v); + uint32_t val = vlapic_get_reg(vlapic, offset); + + if ( !vlapic_x2apic_mode(vlapic) ) + return vlapic_reg_write(v, offset, val); + + if ( offset != APIC_SELF_IPI ) + return X86EMUL_UNHANDLEABLE; + + return vlapic_reg_write(v, APIC_ICR, APIC_DEST_SELF | (uint8_t)val); } int hvm_x2apic_msr_write(struct vcpu *v, unsigned int msr, uint64_t msr_content) @@ -865,16 +850,33 @@ int hvm_x2apic_msr_write(struct vcpu *v, switch ( offset ) { - int rc; + case APIC_TASKPRI: + case APIC_EOI: + case APIC_SPIV: + case APIC_CMCI: + case APIC_LVTT ... APIC_LVTERR: + case APIC_TMICT: + case APIC_TMCCT: + case APIC_TDCR: + break; case APIC_ICR: - rc = vlapic_reg_write(v, APIC_ICR2, (uint32_t)(msr_content >> 32)); - if ( rc ) - return rc; + vlapic_set_reg(vlapic, APIC_ICR2, msr_content >> 32); break; - case APIC_ICR2: - return X86EMUL_UNHANDLEABLE; + case APIC_SELF_IPI: + offset = APIC_ICR; + msr_content = APIC_DEST_SELF | (uint8_t)msr_content; + break; + + case APIC_ESR: + if ( msr_content ) + { + printk(XENLOG_G_WARNING "%pv: non-zero (%lx) LAPIC ESR write\n", + v, msr_content); + default: + return X86EMUL_UNHANDLEABLE; + } } return vlapic_reg_write(v, offset, (uint32_t)msr_content); @@ -884,7 +886,10 @@ static int vlapic_range(struct vcpu *v, { struct vlapic *vlapic = vcpu_vlapic(v); unsigned long offset = addr - vlapic_base_address(vlapic); - return (!vlapic_hw_disabled(vlapic) && (offset < PAGE_SIZE)); + + return !vlapic_hw_disabled(vlapic) && + !vlapic_x2apic_mode(vlapic) && + (offset < PAGE_SIZE); } const struct hvm_mmio_handler vlapic_mmio_handler = { @@ -893,10 +898,12 @@ const struct hvm_mmio_handler vlapic_mmi .write_handler = vlapic_write }; -void vlapic_msr_set(struct vlapic *vlapic, uint64_t value) +bool_t vlapic_msr_set(struct vlapic *vlapic, uint64_t value) { if ( (vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_ENABLE ) { + if ( unlikely(value & MSR_IA32_APICBASE_EXTD) ) + return 0; if ( value & MSR_IA32_APICBASE_ENABLE ) { vlapic_reset(vlapic); @@ -905,10 +912,15 @@ void vlapic_msr_set(struct vlapic *vlapi } else { + if ( unlikely(vlapic_x2apic_mode(vlapic)) ) + return 0; vlapic->hw.disabled |= VLAPIC_HW_DISABLED; pt_may_unmask_irq(vlapic_domain(vlapic), NULL); } } + else if ( !(value & MSR_IA32_APICBASE_ENABLE) && + unlikely(value & MSR_IA32_APICBASE_EXTD) ) + return 0; vlapic->hw.apic_base_msr = value; @@ -923,6 +935,8 @@ void vlapic_msr_set(struct vlapic *vlapi HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr); + + return 1; } uint64_t vlapic_tdt_msr_get(struct vlapic *vlapic) @@ -1206,6 +1220,10 @@ static int lapic_load_hidden(struct doma if ( hvm_load_entry_zeroextend(LAPIC, h, &s->hw) != 0 ) return -EINVAL; + if ( !(s->hw.apic_base_msr & MSR_IA32_APICBASE_ENABLE) && + unlikely(vlapic_x2apic_mode(s)) ) + return -EINVAL; + vmx_vlapic_msr_changed(v); return 0; --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3096,8 +3096,7 @@ void vmx_vmexit_handler(struct cpu_user_ break; case EXIT_REASON_APIC_WRITE: - if ( vmx_handle_apic_write() ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + vmx_handle_apic_write(); break; case EXIT_REASON_ACCESS_GDTR_OR_IDTR: --- a/xen/include/asm-x86/hvm/vlapic.h +++ b/xen/include/asm-x86/hvm/vlapic.h @@ -106,7 +106,7 @@ void vlapic_destroy(struct vcpu *v); void vlapic_reset(struct vlapic *vlapic); -void vlapic_msr_set(struct vlapic *vlapic, uint64_t value); +bool_t vlapic_msr_set(struct vlapic *vlapic, uint64_t value); void vlapic_tdt_msr_set(struct vlapic *vlapic, uint64_t value); uint64_t vlapic_tdt_msr_get(struct vlapic *vlapic);