From f2bf190255c8f872d15063d7f8a6382c279e312d Mon Sep 17 00:00:00 2001 From: Brandon Perez Date: Mon, 20 Jul 2015 17:56:49 -0400 Subject: [PATCH 1/3] This patch adds in IO mappings for several devices which are not explicitly laid out in the device tree, and mappings for DRA72x specific regions that are not devices. In the ARM virtualization setup, the virtual memory uses a 2-stage translation. The guest OS VM performs a virtual address translation to an intermediate physical address, which is still not a true physical memory address. The Xen hypervisor VM then translates this IPA to an actual physical address. Thus, in order for a guest OS (even Dom0) to access a physical address, Xen must explicitly setup a mapping in its VM for the guest OS to access this location. Several devices were missing from the device tree, so Xen was unware of the need to map their MMIO registers. Thus, the platform has specific_mapping() function, which patches up these holes. The OMAP5 specific mapping function is missing a few items that DRA72x chips need, so these were added in. --- xen/arch/arm/platforms/omap5.c | 27 +++++++++++++++++++++++++++ xen/include/asm-arm/platforms/omap5.h | 3 +++ 2 files changed, 30 insertions(+) diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c index e7bf30d..3c6495a 100644 --- a/xen/arch/arm/platforms/omap5.c +++ b/xen/arch/arm/platforms/omap5.c @@ -120,6 +120,32 @@ static int omap5_specific_mapping(struct domain *d) return 0; } +/* Additional mappings for dom0 (not in the DTS) */ +static int dra7_specific_mapping(struct domain *d) +{ + /* Map the PRM module */ + map_mmio_regions(d, paddr_to_pfn(OMAP5_PRM_BASE), 2, + paddr_to_pfn(OMAP5_PRM_BASE)); + + /* Map the PRM_MPU */ + map_mmio_regions(d, paddr_to_pfn(OMAP5_PRCM_MPU_BASE), 1, + paddr_to_pfn(OMAP5_PRCM_MPU_BASE)); + + /* Map the Wakeup Gen */ + map_mmio_regions(d, paddr_to_pfn(OMAP5_WKUPGEN_BASE), 1, + paddr_to_pfn(OMAP5_WKUPGEN_BASE)); + + /* Map the on-chip SRAM */ + map_mmio_regions(d, paddr_to_pfn(OMAP5_SRAM_PA), 32, + paddr_to_pfn(OMAP5_SRAM_PA)); + + /* Map GPMC address space for NAND flash. */ + map_mmio_regions(d, paddr_to_pfn(OMAP5_GPMC_PA), 65536, + paddr_to_pfn(OMAP5_GPMC_PA)); + + return 0; +} + static int __init omap5_smp_init(void) { void __iomem *wugen_base; @@ -171,6 +197,7 @@ PLATFORM_START(dra7, "TI DRA7") .init_time = omap5_init_time, .cpu_up = cpu_up_send_sgi, .smp_init = omap5_smp_init, + .specific_mapping = dra7_specific_mapping, .dom0_gnttab_start = 0x4b000000, .dom0_gnttab_size = 0x20000, diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h index c559c84..d87e7d2 100644 --- a/xen/include/asm-arm/platforms/omap5.h +++ b/xen/include/asm-arm/platforms/omap5.h @@ -20,6 +20,9 @@ #define OMAP_AUX_CORE_BOOT_0_OFFSET 0x800 #define OMAP_AUX_CORE_BOOT_1_OFFSET 0x804 +#define OMAP5_GPMC_PA 0x01000000 +#define OMAP5_TILER_PA 0x60000000 + #endif /* __ASM_ARM_PLATFORMS_OMAP5_H */ /* -- 1.7.9.5