ns16550: limit mapped MMIO size There's no point in mapping more than the memory we actually may need to touch, and in fact the too large region could actually extend into another device's one (which currently is benign on x86 since only a single page gets mapped anyway, but which is a latent bug on ARM whenever PCI support gets enabled there). Signed-off-by: Jan Beulich --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -931,6 +931,8 @@ pci_uart_config (struct ns16550 *uart, i uart->io_base += bar_idx * uart_param[p].uart_offset; if ( uart_param[p].base_baud ) uart->clock_hz = uart_param[p].base_baud * 16; + size = max(8U << uart_param[p].reg_shift, + uart_param[p].uart_offset); /* Set device and MMIO region read only to Dom0 */ uart->enable_ro = 1; break;