x86/MSI: handle both MSI-X and MSI in cfg space write intercept In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests") I neglected to consider devices allowing for both MSI and MSI-X to be used (not at the same time of course): The MSI-X part of the intercept logic needs to fall through to the MSI one when the access is outside the MSI-X capability bounds. Signed-off-by: Jan Beulich --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct PCI_CAP_ID_MSIX); ASSERT(pos); - if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 ) - return 0; + if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 ) + { + if ( reg != msix_control_reg(pos) || size != 2 ) + return -EACCES; - if ( reg != msix_control_reg(pos) || size != 2 ) - return -EACCES; + pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); + if ( pdev->msix->host_maskall ) + *data |= PCI_MSIX_FLAGS_MASKALL; - pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); - if ( pdev->msix->host_maskall ) - *data |= PCI_MSIX_FLAGS_MASKALL; - - return 1; + return 1; + } } entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);