RE: [Xen-ia64-devel] Strange code in vmx_ivt.S

["Xu, Anthony" <anthony.xu@xxxxxxxxx>]

>
>can someone (from Intel ?) comment this code:
>
>// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
>ENTRY(vmx_alt_itlb_miss)
>    VMX_DBG_FAULT(3)
>    mov r31 = pr
>    mov r29=cr.ipsr;
>    ;;
>    tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
>(p7)br.spnt vmx_fault_3
>vmx_alt_itlb_miss_1:
>    mov r16=cr.ifa    // get address that caused the TLB miss
>    ;;
>    tbit.z p6,p7=r16,63  //*********************************
>(p6)br.spnt vmx_fault_3
>    ;;
>
>I don't understand the tbit.z (***) test.  The code after the br does
itc
>in identity-mapped area.  But testing bit 63 is not enough.

This code is used for early debug, and it will not branch.
The check can be removed.

Thanks,
Anthony

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