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RE: [Xen-ia64-devel] Question about vmx_ivt.S


  • To: "Tristan Gingold" <tgingold@xxxxxxx>
  • From: "Xu, Anthony" <anthony.xu@xxxxxxxxx>
  • Date: Wed, 10 Oct 2007 09:09:10 +0800
  • Cc: Xen-ia64-devel <xen-ia64-devel@xxxxxxxxxxxxxxxxxxx>
  • Delivery-date: Tue, 09 Oct 2007 18:10:07 -0700
  • List-id: Discussion of the ia64 port of Xen <xen-ia64-devel.lists.xensource.com>
  • Thread-index: AcgK2U4lZjRktIrYTXK/RHsiJLPEGwAALNew
  • Thread-topic: [Xen-ia64-devel] Question about vmx_ivt.S

Hi Tristan,

You are right, mf can be deleted.

Thanks
Anthony


>From: Tristan Gingold [mailto:tgingold@xxxxxxx]
>Sent: 2007年10月10日 9:09
>To: Xu, Anthony
>Cc: tgingold@xxxxxxx; Xen-ia64-devel
>Subject: Re: [Xen-ia64-devel] Question about vmx_ivt.S
>
>On Tue, Oct 09, 2007 at 04:23:20PM +0800, Xu, Anthony wrote:
>>
>> VHPT speculative load happens in the same time when tlb_miss handler is
>executing.
>[...]
>>
>> Mf is to make sure that before modifying vhpt entry, vhpt entry must be
>disabled, otherwise VHPT walker hardware may see enabled half modified vhpt
>entry(definitely wrong entry), and load it into TLB cache.
>
>I do understand why the VHPT entry must be disabled before being modified
>and
>enabled after.  I do not understand why the MF is required.
>>
>>
>> Notice
>> For example, Write2 is after write1,
>> Write2 may be visible before write1.
>
>'Visible' is defined only wrt other processor.  But only the local
>processor
>will use the VHPT.  Therefore, no need to make the write visible.
>
>In your example, if the memory is read between write1 and write2, the value
>will *always* be the value of write1. (if no other processor modifies the
>memory at the address).
>
>Tristan.

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