[Xen-ia64-devel] [PATCH][GFW] support windows 2008

[Kouya Shimura <kouya@xxxxxxxxxxxxxx>]

Hi Tristan,

Here is a patch to support windows 2008 (aka Longhorn).
I don't know EFI spec well and this patch might do something wrong.
But I succeed in installing and running windows 2008 with this patch.

This patch does:
- pin mapping into tr[0] for IVT
- handling alt TLB miss. implementing identity mappping.
- ignoring unaligned reference exception when it is speculated.

If there is no problem, please apply.

Thanks,
Kouya

Signed-off-by: Kouya Shimura <kouya@xxxxxxxxxxxxxx>

diff -r 8ecccd88813c edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s
--- a/edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s       Thu Oct 11 02:09:46 
2007 +0200
+++ b/edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s       Mon Oct 15 17:31:47 
2007 +0900
@@ -24,8 +24,38 @@ VECTOR(0x0000)       // VHPT Translation
 VECTOR(0x0000) // VHPT Translation
 VECTOR(0x0400)  // Instruction TLB
 VECTOR(0x0800)  // Data TLB
-VECTOR(0x0c00)  // Alt instruction TLB
-VECTOR(0x1000)  // Alt data TLB
+//VECTOR(0x0c00)  // Alt instruction TLB
+       .org base + 0xc00
+       mov SCRATCH_REG1=cr.ifa
+       mov SCRATCH_REG2=0x661 // AR=3,PL=0(RWX),D,A,P
+       ;;
+       mov SCRATCH_REG3=14<<2 // pagesize=16KB
+       dep SCRATCH_REG2=SCRATCH_REG2,SCRATCH_REG1,0,12
+       movl SCRATCH_REG4=(1<<50)-1
+       ;;
+       mov cr.itir=SCRATCH_REG3
+       and SCRATCH_REG2=SCRATCH_REG4,SCRATCH_REG2
+       ;;
+       itc.i SCRATCH_REG2
+       ;;
+       rfi
+       ;;
+//VECTOR(0x1000)  // Alt data TLB
+       .org base + 0x1000
+       mov SCRATCH_REG1=cr.ifa
+       mov SCRATCH_REG2=0x661 // AR=3,PL=0(RWX),D,A,P
+       ;;
+       mov SCRATCH_REG3=14<<2 // pagesize=16KB
+       dep SCRATCH_REG2=SCRATCH_REG2,SCRATCH_REG1,0,12
+       movl SCRATCH_REG4=(1<<50)-1
+       ;;
+       mov cr.itir=SCRATCH_REG3
+       and SCRATCH_REG2=SCRATCH_REG4,SCRATCH_REG2
+       ;;
+       itc.d SCRATCH_REG2
+       ;;
+       rfi
+       ;;
 VECTOR(0x1400)  // Data nested TLB
 VECTOR(0x1800)  // Instruction key miss
 VECTOR(0x1c00)  // Data key miss
@@ -51,7 +81,24 @@ VECTOR(0x5700)  // Speculation
 VECTOR(0x5700)  // Speculation
 VECTOR(0x5800)  //
 VECTOR(0x5900)  // Debug
-VECTOR(0x5a00)  // Unaligned reference
+//VECTOR(0x5a00)  // Unaligned reference
+       .org base + 0x5a00
+       mov PR_REG=pr
+       mov SCRATCH_REG1=cr.isr
+       mov SCRATCH_REG2=cr.ipsr
+       ;; 
+       tbit.z p6,p7=SCRATCH_REG1,36 // isr.sp?
+       dep SCRATCH_REG2=-1,SCRATCH_REG2,43,1 // ipsr.ed=1
+       ;;
+(p6)   br.sptk.few 1f  
+(p7)   mov cr.ipsr=SCRATCH_REG2
+       ;; 
+       rfi
+       ;;
+1:
+       mov pr=PR_REG,-1
+       mov SCRATCH_REG1=0x5a00
+       br.cond.sptk.few HookHandler
 VECTOR(0x5b00)  // Unsupported data reference
 VECTOR(0x5c00)  // Floating-point fault
 VECTOR(0x5d00)  // Floating-point trap
@@ -866,6 +913,16 @@ _start:
        movl r8=sale_entry
        mov ar.bspstore=r2
        ;;
+       /* pin mapping into tr[0] for IVT */
+       mov r2=16<<2 // 64KB
+       movl r4=(1<<52)|0x661 // ED,AR=3,PL=0(RWX),D,A,P
+       ;;
+       or r4=r11,r4
+       mov cr.itir=r2
+       mov cr.ifa=r11
+       ;;
+       itr.i itr[r0]=r4
+       ;;
        srlz.d
        //mov ar.rsc=3  // eager mode
        ld8  r9=[r8]    // Read SEC entry descriptor

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